RTA Processing of W-Polycide Dual-Gate Sub-Micron Structures for Low-Voltage CMOS Technology

1996 ◽  
Vol 429 ◽  
Author(s):  
J. Bevk ◽  
M. Furtsch ◽  
G. E. Georgiou ◽  
S. J. Hillenius ◽  
D. Schielein ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Atomic Diffusion ◽  
Cross Diffusion ◽  
Critical Issues ◽  
Simple Processing ◽  
Dual Gate ◽  
Boron Penetration

AbstractDeep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n+/p+ poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1Å to ∼30μm. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. We show that in devices with W-polycide dual-gat:e structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e. g., low-temperature recrystallization of a-Si layer and selective nitrogen coimplants). The RTA step, in particular, ensures thai: the boron activation in the p+ poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (<30mV), and excellent device characteristics.

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Chung-Yu Wu ◽  
Hun-Hsien Chang ◽  
Chien-Chang Huang ◽  
Chau-Neng Wu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron

NEW ROBUST n+/p+ DUAL-GATE CMOS TECHNOLOGY OPTIMIZED FOR LOW POWER OPERATION

1994 ◽  
Vol 05 (02) ◽  
pp. 135-143 ◽  
Author(s):  
D.C.H. YU ◽  
K.H. LEE ◽  
A. KORNBLIT ◽  
C.C. FU ◽  
R.H. YAN ◽  
...  
Keyword(s):  
Low Power ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Design Rule ◽  
Gate Stack ◽  
Thermal Budget ◽  
Critical Issues ◽  
Dual Gate ◽  
Power Operation ◽  
Symmetric Surface

A novel optimized dual-gate technology ( p +-gate for PMOS and n +-gate for NMOS) for symmetric surface-channel CMOS devices is developed to fabricate low-power components. This technology features a WSi x-polycide gate dopant drive-out technique to dope the n + and p + gate and a TiN shunt process to connect the dual-gate. We demonstrate that the critical issues associated with a dual-gate technology are resolved by this new and robust technology. There are no design rule penalties for gate layout width or n + to p + source/drain separation with this process. The CMOS devices are scalable even down to 0.1 μm gates due to the design rule advantages. No degradation is measured in device characteristics due to the diffusion of gate dopants either laterally between an opposite type of gate or vertically through the gate stack. Ion penetration during gate implant is also effectively suppressed by the new gate stack. No degradation in gate sheet resistance, R s, is detected. The most severe annealing condition tested in this work is 900°C for 30 minutes. Therefore, plenty of thermal budget is allowed is this technology. This improvement not only adds to the robustness of the technology but also increases the conductance of the gate runner.

W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology

2002 ◽  
Author(s):  
J. Bevk ◽  
G.E. Georgiou ◽  
M. Frei ◽  
P.J. Silverman ◽  
E.J. Lloyd ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Gate Structure ◽  
Dual Gate

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

2013 ◽  
Vol 22 (06) ◽  
pp. 1350048 ◽  
Author(s):  
SARAVANAN RAMAMOORTHY ◽  
HAIBO WANG
Keyword(s):  
Memory Effect ◽  
Threshold Voltage ◽  
Power Supply ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Design Modification ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Near Threshold

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

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