Impact of 0.25 [micro sign]m dual gate oxide thickness CMOS process on flicker noise performance of multifingered deep-submicron MOS devices

2001 ◽  
Vol 148 (6) ◽  
pp. 312 ◽  
Author(s):  
K.W. Chew ◽  
K.S. Yeo ◽  
S.-F. Chu ◽  
Y.M. Wang
Keyword(s):  
Flicker Noise ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Cmos Process ◽  
Noise Performance ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Dual Gate

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Short Channel ◽  
Gate Oxide Thickness ◽  
Process Effects ◽  
Dual Gate ◽  
N Dose ◽  
The Impact

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

M.O.S. Transistors with > 1 μm Thick Gate Oxide for Ionizing Radiation Dosimetry

1993 ◽  
Vol 302 ◽  
Author(s):  
F. Gessinn ◽  
G. Sarrabayrouse
Keyword(s):  
Ionizing Radiation ◽  
Radiation Dosimetry ◽  
Temperature Response ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
The Other ◽  
Mos Transistors ◽  
Major Focus ◽  
Mos Devices ◽  
Gate Oxide Thickness

ABSTRACTThe effects of ionizing radiation on MOS transistors with gate oxide thickness up to 2 μm have been investigated. The major focus of workers in this area has been on the hardening techniques of technologies. On the other side, our goal is to use MOS devices to reach higher sensitivities in order to detect small amounts of dose. Therefore, sensitivity as well as temperature response in the mil-std range and stability of the dosimeters have been studied.

PCA Characterization of Residual Subsurface Damage After Silicon Wafer Mirror Polishing and its Removal

1999 ◽  
Vol 566 ◽  
Author(s):  
Y. Ogita ◽  
K. Kobayashi ◽  
H. Daio
Keyword(s):  
Direct Evidence ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Mos Devices ◽  
Catching Up ◽  
Gate Oxide Thickness ◽  
Damage Depth ◽  
Thin Gate Oxide ◽  
Straight Lines

Residual subsurface damages introduced by mirror polishing into Si CZ wafers degrade GOI in ULSI MOS devices. A removal of the damage throughout 9 times SC1 cleaning was systematically characterized as correlated between PCA signals measured by noncontact UV/mmwave technique, GOI at 10MV/cm for MOS diodes with a thin gate-oxide thickness of 10nm, surface microroughness Ra measured by AFM. The same characterization was carried out for epitaxial wafers, as reference. Degraded GOI and PCA signal were recovered throughout 3 times SC1 cleaning and did not depend on Ra of 0.1–0.2 nm, which led to that the damage causes the degradation of GOI, but it can be removed by 3 times SC1 cleaning, and the damage depth was about 21nm. Further, the PCA signal well reflects to removal of the damage and degradation of GOI so that it can be a monitor for characterizing the removal and GOI. Direct observation of the damage using OSDA was carried out for the epitaxial wafer polished and SC1 cleaned. The OSDA indicated an image involving straight lines which disappeared after 3 times SC1 cleaning. This gave a direct evidence for catching up it by PCA and existence of residual subsurface damages.

LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS

2002 ◽  
Vol 11 (06) ◽  
pp. 575-600 ◽  
Author(s):  
KAUSHIK ROY ◽  
SAIBAL MUKHOPADHYAY ◽  
HAMID MAHMOODI-MEIMAND
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Cmos Circuits ◽  
Weak Inversion ◽  
Gate Oxide Thickness ◽  
Gate Oxide Tunneling

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.

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