The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping

2005 ◽  
Vol 864 ◽  
Author(s):  
Jong-Heon Yang ◽  
In-Bok Baek ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Sungkweon Baek ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Oxide Interface ◽  
Substrate Heating ◽  
Plasma Doping ◽  
Device Reliability ◽  
Research Show

AbstractWe fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350··, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices.

Thermal annealing effects on La2Hf2O7:Eu3+ nanoparticles: a curious case study of structural evolution and site-specific photo- and radio-luminescence

2018 ◽  
Vol 5 (10) ◽  
pp. 2508-2521 ◽  
Author(s):  
Santosh K. Gupta ◽  
Jose P. Zuniga ◽  
Maya Abdou ◽  
Yuanbing Mao
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Structural Evolution ◽  
Site Specific ◽  
Red Emission ◽  
Orange Emission ◽  
Annealing Effects

High temperature annealed La2Hf2O7:Eu3+ nanoparticles favor tunneling of Eu3+ to symmetric sites showing orange emission, whereas low temperature annealed samples favor red emission.

Comparison of 4H-SiC MOSFETs on (0001), (000-1) and (11-20) Oriented Substrates

2009 ◽  
Vol 615-617 ◽  
pp. 785-788 ◽  
Author(s):  
Harsh Naik ◽  
K. Tang ◽  
T. Marron ◽  
T. Paul Chow ◽  
Jody Fronheiser
Keyword(s):  
Low Temperature ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Field Effect ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Field Effect Mobility

The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Effect of Graphite Cap for Implant Activation on Inversion Channel Mobility in 4H-SiC MOSFETs

2009 ◽  
Vol 615-617 ◽  
pp. 773-776 ◽  
Author(s):  
Harsh Naik ◽  
K. Tang ◽  
T. Paul Chow
Keyword(s):  
Low Temperature ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Field Effect ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
Inversion Channel

The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Comparison of Gate Oxide Processing Techniques for Thin Dielectric Films

1996 ◽  
Vol 446 ◽  
Author(s):  
Pat Schay ◽  
Fuyu Lin ◽  
Sergio Ajuria ◽  
John Stih
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Electrical Performance ◽  
Dielectric Films ◽  
Total Thickness ◽  
Large Area ◽  
Processing Techniques ◽  
Thin Dielectric Films

AbstractThis paper focuses on establishing a baseline for thin dielectric processes including: low temperature, dilute, stacked (TEOS), oxynitride, and high temperature annealed (grow‐anneal‐grow) oxidation. 105Å (total thickness) gate dielectrics were grown or deposited for this study. The stack oxide showed the highest Vbd yields for both large‐area and edge‐intensive capacitors, but the poorest Qbd. The N2O oxide yielded mediocre Vbd and Qbd. The low temperature and dilute oxides showed early breakdowns, but acceptable Qbd. 900°C thermal gate oxide showed slightly better average Vbd than low temperature and dilute oxides but comparable Qbd. The high temperature annealed oxide appears to have the best electrical performance, but the worst uniformity.

High-Quality Gate-Oxide Films for Low-Temperature Fabricated Poly-Si TFTs

1989 ◽  
Vol 146 ◽  
Author(s):  
Shiro Suyama ◽  
Akio Okamoto ◽  
Seiiti Shirai ◽  
Tadashi Serikawa
Keyword(s):  
Low Temperature ◽  
Silicon Oxide ◽  
Oxide Films ◽  
Drain Current ◽  
Gate Oxide ◽  
Breakdown Field ◽  
Subthreshold Slope ◽  
High Quality ◽  
Argon Mixture ◽  
Sputter Deposited

ABSTRACTHigh-quality gate-oxide films for poly-Si TFTs (Thin Film Transistors) are successfully produced by oxygen-argon sputter deposition at a low temperature (200°C). Silicon-oxide films that are sputter-deposited in an oxygen-argon mixture has higher resistivity and breakdown field than films that are sputterdeposited only in argon and thermal oxides grown on poly-Si. Moreover, TFT field-effect mobilities are considerably improved by mixing oxygen into the sputtering gas, resulting in 350 cm2 /V.sec. Subthreshold slope and threshold voltage are also reduced to 5.5 V and 0.8 V/decade. A temperature-dependence measurement of the drain current shows that these improvements in TFT characteristics result from a lowering of the barrier height at the poly-Si grain boundaries, indicating a reduction in the trap density at these boundaries. Results confirm the usefulness of gate-oxide films that are sputter-deposited in an oxygen-argon mixture, for lowtemperature fabricated poly-Si TFTs.

Effect of Si Implantation and Rapid Thermal Annealing on GaAs/AlGaAs Superlattice Disordering.

1986 ◽  
Vol 77 ◽  
Author(s):  
J. D. Flood ◽  
G. Bahir ◽  
J. L. Merz ◽  
J. Kobayashi ◽  
T. Fukunaga ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Electron Gas ◽  
Average Composition ◽  
Furnace Annealing ◽  
Strong Emission ◽  
Disordered Layer ◽  
Low Temperature Photoluminescence

ABSTRACTThe enhanced disordering of GaAs/AlGaAs superlattices by diffusion of Zn or Si has been reported by many authors. In the case of Si diffusion, the Si can be introduced during epitaxial growth, by implantation, or by diffusion from a sputtered Si mask. In this paper ion implantation is investigated, and the effect of rapid thermal annealing (RTA), used to minimize Si diffusion while eliminating the implant damage, is compared with furnace annealing (FA). Using low temperature photoluminescence (PL) and SIMS, it is found that no disordering of a GaAs/Al0.5Ga0.5As superlattice takes place for a 2 sec anneal at 900°C, and very minimal partial disordering is observed (reproducibly) for a 10 sec anneal at 970°C. This is in sharp contrast with the FA case (850°C for 30 min), for which significant disordering occurs. The PL spectra show luminescence from both GaAs and GaAs/Al0.5Ga0.5As layers in the case of high-temperature RTA suggesting that recrystallization has occurred without disorder, whereas strong emission is observed after FA which corresponds to a disordered layer of average-composition GaAs/Al0.15Ga0.25As In both cases, PL indicates that annealing of the implant damage has occurred. Thus, damage can be eliminated either with or without disordering the superlattice by using FA or RTA, respectively. This is important for 2-D electron gas structures, for which no broadening of the hetero-interface is desired.

High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack

2018 ◽  
Vol 924 ◽  
pp. 494-497 ◽  
Author(s):  
Jesus Urresti ◽  
Faiz Arith ◽  
Konstantin Vassilevski ◽  
Amit Kumar Tiwari ◽  
Sarah Olsen ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
High Mobility ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Stack ◽  
Mos Capacitors ◽  
Channel Mobility

We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DITand channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

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