Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

2000 ◽  
Author(s):  
Yunqiang Zhang ◽  
Chock H. Gan ◽  
Xi Li ◽  
James Lee ◽  
David Vigar ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Device Performance ◽  
Oxide Reliability ◽  
Dual Gate ◽  
Boron Penetration

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

Tunneling Effects in NH3 Annealed 4H-SiC Trench MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 652-658
Author(s):  
Judith Berens ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Effective Activation Energy ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Performance ◽  
Trap Level ◽  
Effective Activation ◽  
Oxide Reliability ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Mos Structures

The interface between the gate oxide and silicon carbide (SiC) has a strong influence on the performance and reliability of SiC MOSFETs and thus, requires special attention. In order to reduce charge trapping at the interface, post oxidation anneals (POAs) are conventionally applied. However, these anneals do not only influence the device performance, such as mobility and on-resistance, but also the gate oxide reliability. We study the oxide tunneling mechanisms of NH3 annealed 4H-SiC trench MOSFET test structures and compare them to devices which received a NO POA. We show that 3 different mechanisms, namely trap assisted tunneling (TAT), Fowler-Nordheim (FN) tunneling and charge trapping are found for NH3 annealed MOS structures whereas only FN-tunneling is observed in NO annealed devices.The tunneling barrier suggest a trap level with an effective activation energy of 382 meV to enable TAT.

Impact of boron penetration on gate oxide reliability and device lifetime in p+-poly PMOSFETs

1997 ◽  
Vol 36 (1-4) ◽  
pp. 313-316 ◽  
Author(s):  
B.Y. Kim ◽  
I.M. Liu ◽  
H.F. Luan ◽  
M. Gardner ◽  
J. Fulford ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
Device Lifetime ◽  
Boron Penetration

A Universal Relationship between Boron Penetration and Gate Oxide Reliability for Surface Channel PMOSFET

1996 ◽  
Author(s):  
M. Arai ◽  
T. Nakabayashi ◽  
T. Yabu ◽  
I. Matsuo ◽  
A. Kanda ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
Universal Relationship ◽  
Boron Penetration

Boron penetration effect on gate oxide reliability of 50 Å PMOS devices

2000 ◽  
Vol 40 (4-5) ◽  
pp. 637-640 ◽  
Author(s):  
Carl Kyono ◽  
Tomasz Brożek ◽  
Vida Ilderem
Keyword(s):  
Gate Oxide ◽  
Penetration Effect ◽  
Oxide Reliability ◽  
Boron Penetration
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