Techniques for minimizing power dissipation in scan and combinational circuits during test application

1998 ◽  
Vol 17 (12) ◽  
pp. 1325-1333 ◽  
Author(s):  
V. Dabholkar ◽  
S. Chakravarty ◽  
I. Pomeranz ◽  
S. Reddy
Keyword(s):  
Power Dissipation ◽  
Combinational Circuits ◽  
Test Application

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

2017 ◽  
Vol 9 (02) ◽  
pp. 93-96
Author(s):  
Vinay Kumar Verma ◽  
Neeraj Kumar Misra
Keyword(s):  
Information Flow ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Combinational Circuits ◽  
Analysis And Design ◽  
Critical Issues ◽  
Simulation Purpose ◽  
And Performance ◽  
Synthesis Approach ◽  
Computing Speed

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

scholarly journals Low Power Built-In Self-Test Schemes for Array and Booth Multipliers

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 431-448 ◽  
Author(s):  
D. Bakalist ◽  
X. Kavousianos ◽  
H. T. Vergos ◽  
D. Nikolos ◽  
G. Ph. Alexiou
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Average Power ◽  
Total Power ◽  
Power Efficient ◽  
Test Application ◽  
Low Power Dissipation ◽  
Recent Trends ◽  
Self Test ◽  
Built In Self Test

Recent trends in IC technology have given rise to a new requirement, that of low power dissipation during testing, that Built-In Self-Test (BIST) structures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modified Booth multipliers, in this paper we propose new power-efficient BIST structures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be reduced from 29.3% to 54.9%, while the average power per test vector applied can be reduced from 5.8% to 36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST schemes implementation area is small.

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