scholarly journals Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing

2000 ◽  
Vol 147 (5) ◽  
pp. 313 ◽  
Author(s):  
N. Nicolici ◽  
B.M. Al-Hashimi ◽  
A.C. Williams
Keyword(s):  
Power Dissipation ◽  
Sequential Circuits ◽  
Primary Input ◽  
Test Application ◽  
Full Scan

Design of a novel quantum reversible ternary up-counter

2015 ◽  
Vol 13 (05) ◽  
pp. 1550038 ◽  
Author(s):  
Pouran Houshmand ◽  
Majid Haghparast
Keyword(s):  
Power Dissipation ◽  
Reversible Logic ◽  
Sequential Circuits ◽  
Utilization Rate ◽  
Time And Space ◽  
Space Utilization ◽  
Flip Flop ◽  
New Approach ◽  
Combinational And Sequential Circuits ◽  
Better Than

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.

Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control

2020 ◽  
Vol 18 (3) ◽  
pp. 210-215
Author(s):  
Shubham Tayal ◽  
Sunil Jadav
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Joint Effect ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Cmos Circuits ◽  
Trade Offs ◽  
Self Bias ◽  
Semiconductor Circuits

Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.

FLOSPAT: Fault Localization by Sensitized Path Transformation

1996 ◽  
Author(s):  
M.W. Heath ◽  
W. Maly
Keyword(s):  
Boolean Functions ◽  
Fault Localization ◽  
Fault Model ◽  
Sequential Circuits ◽  
Fault Identification ◽  
Identification Algorithm ◽  
Path Tracing ◽  
Full Scan ◽  
Diagnostic Resolution ◽  
Test Vectors

Abstract This paper describes a fault identification algorithm for combinational and full-scan sequential circuits called FLOSPAT - Fault Localization by Sensitized Path Transformation [1,2]. The goal of fault identification is to localize a fault to the fewest possible gates and to determine the Boolean functions realized by those gates. Instead of choosing a fault model, FLOSPAT uses fault-independent sensitized path tracing [3] to localize functional deviations. Sensitized path transformation is used to adaptively generate test vectors which improve the diagnostic resolution. The output of FLOSPAT is used for physical defect diagnosis by cross-referencing gate-level defect dictionaries generated by the contamination-defect-fault mapper CODEF [4,5,6].

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