Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation

1992 ◽  
Vol 11 (3) ◽  
pp. 373-383 ◽  
Author(s):  
S. Devadas ◽  
K. Keutzer ◽  
J. White
Keyword(s):  
Boolean Function ◽  
Power Dissipation ◽  
Combinational Circuits

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

2017 ◽  
Vol 9 (02) ◽  
pp. 93-96
Author(s):  
Vinay Kumar Verma ◽  
Neeraj Kumar Misra
Keyword(s):  
Information Flow ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Combinational Circuits ◽  
Analysis And Design ◽  
Critical Issues ◽  
Simulation Purpose ◽  
And Performance ◽  
Synthesis Approach ◽  
Computing Speed

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

scholarly journals Masking of Internal Nodes Faults Based on Applying of Incompletely Specified Boolean Functions

2020 ◽  
Vol 20 (4) ◽  
pp. 517-526
Author(s):  
Angela Yu. Matrosova ◽  
◽  
Victor A. Provkin ◽  
Valentina V. Andreeva ◽  
◽  
...  
Keyword(s):  
Boolean Function ◽  
Circuit Design ◽  
Boolean Functions ◽  
Internal Node ◽  
Sequential Circuits ◽  
Combinational Circuits ◽  
Suggested Approach ◽  
System A ◽  
Internal Fault ◽  
The Given

Combinational circuits (combinational parts of sequential circuits) are considered. Masking of internal nodes faults with applying sub-circuit, inputs of which are connected to the circuit inputs and outputs — to the circuit proper internal nodes, is suggested. The algorithm of deriving incompletely specified Boolean function for an internal node of the circuit based on using operations on ROBDDs is described. Masking circuit (patch circuit) design for the given internal fault nodes is reduced to covering of the system of incompletely specified Boolean functions corresponding to the fault nodes by the proper SoP system. Then the obtained system of completely specified Boolean functions is applied to derive masking circuit by using ABC system (A System for Sequential Synthesis and Verification). Experiments on bench marks show essential cutting of overhead in the frame of the suggested approach.

scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

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