A built-in test circuit for open defects at interconnects between dies in 3D ICs

2012 ◽  
Author(s):  
Widianto ◽  
Hiroyuki Yotsuyanagi ◽  
Akira Ono ◽  
Masao Takagi ◽  
Masaki Hashizume
Keyword(s):  
3D Ics ◽  
Test Circuit ◽  
Open Defects

Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops

2016 ◽  
Author(s):  
Fara Ashikin Binti Ali ◽  
Masaki Hashizume ◽  
Yuki Ikiri ◽  
Hiroyuki Yotsuyanagi ◽  
Shyue-Kung Lu
Keyword(s):  
Boundary Scan ◽  
3D Ics ◽  
Interconnect Test ◽  
Open Defects ◽  
Resistive Open Defects

A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

2015 ◽  
Vol 761 ◽  
pp. 202-207
Author(s):  
Masaki Hashizume ◽  
Shohei Suenaga ◽  
Hiroyuki Yotsuyanagi
Keyword(s):  
Spice Simulation ◽  
Appearance Time ◽  
Test Circuit ◽  
Cmos Ic ◽  
Open Defect ◽  
Supply Current ◽  
Open Defects

A built-in test circuit is proposed to detect an open defect in a CMOS IC by means of appearance time of dynamic supply current of the IC. A layout of an IC embedding the test circuit is designed. It is shown by Spice simulation that an open defect in the IC can be detected with the test circuit.

scholarly journals Electrical Test Method for Interconnect Open Defects in 3D ICs

2012 ◽  
Vol 5 (1) ◽  
pp. 26-33 ◽  
Author(s):  
Tomoaki Konishi ◽  
Hiroyuki Yotsuyanagi ◽  
Masaki Hashizume
Keyword(s):  
Test Method ◽  
Electrical Test ◽  
3D Ics ◽  
Open Defects

scholarly journals A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

2016 ◽  
Vol E99.D (11) ◽  
pp. 2723-2733
Author(s):  
Widiant ◽  
Masaki HASHIZUME ◽  
Shohei SUENAGA ◽  
Hiroyuki YOTSUYANAGI ◽  
Akira ONO ◽  
...  
Keyword(s):  
Interconnect Testing ◽  
Test Circuit ◽  
Open Defects
Sign in / Sign up

Export Citation Format

Share Document