2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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9781538603628

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On-line software-based self-test for ECC of embedded RAM memories

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244443 ◽

2017 ◽

Cited By ~ 1

Author(s):

M. Restifo ◽

P. Bernardi ◽

S. De Luca ◽

A. Sansonetti

Keyword(s):

On Line ◽

Self Test

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Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244437 ◽

2017 ◽

Cited By ~ 3

Author(s):

H Junqi ◽

T. Nandha Kumar ◽

Haider Abbas ◽

Fabrizio Lombardi

Keyword(s):

Simulation Based

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A novel low-overhead fault tolerant parallel-pipelined FFT design

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244461 ◽

2017 ◽

Cited By ~ 1

Author(s):

Yu Xie ◽

Chen Yang ◽

Chuang-An Mao ◽

He Chen ◽

Yi-Zhuang Xie

Keyword(s):

Fault Tolerant ◽

Parallel Pipelined

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Machine learning based test pattern analysis for localizing critical power activity areas

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244464 ◽

2017 ◽

Cited By ~ 6

Author(s):

Harshad Dhotre ◽

Stephan Eggersglus ◽

Mehdi Dehbashi ◽

Ulrike Pfannkuchen ◽

Rolf Drechsler

Keyword(s):

Machine Learning ◽

Pattern Analysis ◽

Test Pattern ◽

Critical Power ◽

Activity Areas

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Investigating the effects of process variations and system workloads on endurance of non-volatile caches

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244430 ◽

2017 ◽

Cited By ~ 1

Author(s):

Amir Mahdi Hosseini Monazzah ◽

Hamed Farbeh ◽

Seyed Ghassem Miremadi

Keyword(s):

Process Variations

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High performance fault tolerance through predictive instruction re-execution

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244459 ◽

2017 ◽

Author(s):

Jyothish Soman ◽

Timothy M. Jones

Keyword(s):

Fault Tolerance ◽

High Performance

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Preventing scan-based side-channel attacks through key masking

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244434 ◽

2017 ◽

Author(s):

Satyadev Ahlawat ◽

Darshit Vaghani ◽

Virendra Singh

Keyword(s):

Side Channel ◽

Side Channel Attacks

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Author index

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244427 ◽

2017 ◽

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Reconfigurable TAP controllers with embedded compression for large test data volume

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244462 ◽

2017 ◽

Cited By ~ 2

Author(s):

Sebastian Huhn ◽

Stephan Eggersglus ◽

Rolf Drechsler

Keyword(s):

Test Data ◽

Data Volume ◽

Embedded Compression

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A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244450 ◽

2017 ◽

Cited By ~ 1

Author(s):

V Gokulkrishnan ◽

V Kamakoti ◽

Nitin Chandrachoodan ◽

Seetal Potluri

Keyword(s):

Fault Diagnosis ◽

Exhaustive Search ◽

Microfluidic Biochips

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2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

On-line software-based self-test for ECC of embedded RAM memories

Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders

A novel low-overhead fault tolerant parallel-pipelined FFT design

Machine learning based test pattern analysis for localizing critical power activity areas

Investigating the effects of process variations and system workloads on endurance of non-volatile caches

High performance fault tolerance through predictive instruction re-execution

Preventing scan-based side-channel attacks through key masking

Author index

Reconfigurable TAP controllers with embedded compression for large test data volume

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications