Defect-state occupation, Fermi-level pinning, and illumination effects on free semiconductor surfaces

1991 ◽  
Vol 43 (5) ◽  
pp. 4071-4083 ◽  
Author(s):  
Robert B. Darling
Keyword(s):  
Fermi Level ◽  
Semiconductor Surfaces ◽  
Defect State ◽  
Fermi Level Pinning

Contactless Electromodulation Characterization of Compound Semiconductor Surfaces and Device Structures

1993 ◽  
Vol 324 ◽  
Author(s):  
J.M. Woodall
Keyword(s):  
Fermi Level ◽  
Electric Fields ◽  
Growth Conditions ◽  
Compound Semiconductor ◽  
Conduction Band Edge ◽  
Semiconductor Surfaces ◽  
Air Exposure ◽  
Fermi Level Pinning ◽  
Characterization Of Properties

AbstractThis paper will review the use of contactless electromodulation methods, such as photoreflectance (PR) and contactless electroreflectance (CER), to characterize the electronic properties of compound semiconductor surfaces exposed to different growth and post-growth conditions. Also the characterization of properties critical to device performance can be evaluated. For example, using PR and CER it has been found that there is a lower density of surface hole traps than electron traps in certain as-grown MBE (001) GaAs samples and that this condition persists even after air exposure. This behaviour is in contrast to other samples, including both bulk and MBE grown (001) surfaces in which the Fermi level is pinned mid-gap for both n- and p-type structures. We also have observed that Ar+ bombardment under UHV conditions results in Fermi level pinning close to the conduction band edge and that thermal annealing restores mid-gap pinning. Finally, using PR we are able to characterize the electric fields and associated doping levels in the emitter and collector regions of heterojunction bipolar transistor structures (fabricated from III-V materials), thus demonstrating the ability to perform inprocess evaluation of important device parameters.

Tomographic investigation of fermi level pinning at focused ion beam milled semiconductor surfaces

2013 ◽  
Vol 103 (26) ◽  
pp. 264104 ◽  
Author(s):  
D. Wolf ◽  
A. Lubk ◽  
A. Lenk ◽  
S. Sturm ◽  
H. Lichte
Keyword(s):  
Fermi Level ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Surfaces ◽  
Fermi Level Pinning

Compound Semiconductor Surfaces and Interfaces: Whence Fermi Level Pinning?

1984 ◽  
Vol 37 ◽  
Author(s):  
Jerry M. Woodall
Keyword(s):  
Fermi Level ◽  
High Speed ◽  
Schottky Contact ◽  
Optoelectronic Device ◽  
Semiconductor Surfaces ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Fermi Level Pinning ◽  
Surfaces And Interfaces ◽  
Special Cases

AbstractExcept for a few special cases, the electrical and optical properties of most III-V semiconductor surfaces and interfaces can be explained in terms of surface Fermi level pinning. However, despite years of research there is no universal agreement on the origin of this pinning. This problem is of more than just academic interest since pinning affects optoelectronic device performance via surface recombination losses, and high speed device performance through uncontrollable ohmic and Schottky contact properties for MESFETs and through a high interface trap density for MISFETs.This talk reviews some of the approaches to the pinning problem and presents some recent results on the role of misfit dislocations in pinning. In particular it will be shown that there are are several models which can explain the usually observed pinning positions. However, we have developed a modified work function model capable of explaining both the usual pinning positions and the experimentally observed exceptions in Schottky barrier height for some metal/semiconductor interfaces. The electrical properties of lattice mismatched GaInAs/GaAs heterojunctions suggest that Fermi level pinning occurs at misfit dislocations.

Fermi level pinning and band bending in δ-doped BaSnO3

2021 ◽  
Vol 118 (5) ◽  
pp. 052101
Author(s):  
Youjung Kim ◽  
Hyeongmin Cho ◽  
Kookrin Char
Keyword(s):  
Fermi Level ◽  
Band Bending ◽  
Fermi Level Pinning

Fermi‐Level Pinning Free High‐Performance 2D CMOS Inverter Fabricated with Van Der Waals Bottom Contacts

2021 ◽  
pp. 2001212
Author(s):  
Tien Dat Ngo ◽  
Zheng Yang ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Inyong Moon ◽  
...  
Keyword(s):  
Fermi Level ◽  
High Performance ◽  
Van Der Waals ◽  
Cmos Inverter ◽  
Fermi Level Pinning

scholarly journals Defect Dominated Charge Transport and Fermi Level Pinning in MoS2/Metal Contacts

2017 ◽  
Vol 9 (22) ◽  
pp. 19278-19286 ◽  
Author(s):  
Pantelis Bampoulis ◽  
Rik van Bremen ◽  
Qirong Yao ◽  
Bene Poelsema ◽  
Harold J. W. Zandvliet ◽  
...  
Keyword(s):  
Fermi Level ◽  
Charge Transport ◽  
Metal Contacts ◽  
Fermi Level Pinning
Sign in / Sign up

Export Citation Format

Share Document