Adsorbate-induced surface states and Fermi-level pinning at semiconductor surfaces

1989 ◽  
Vol 7 (5) ◽  
pp. 1216 ◽  
Author(s):  
Winfried Mönch
Keyword(s):  
Fermi Level ◽  
Surface States ◽  
Semiconductor Surfaces ◽  
Fermi Level Pinning

Fermi-level pinning and intrinsic surface states of Al1−xInxN(101¯0) surfaces

2017 ◽  
Vol 110 (2) ◽  
pp. 022104 ◽  
Author(s):  
V. Portz ◽  
M. Schnedler ◽  
L. Lymperakis ◽  
J. Neugebauer ◽  
H. Eisele ◽  
...  
Keyword(s):  
Fermi Level ◽  
Surface States ◽  
Fermi Level Pinning

MICROSCOPIC UNDERSTANDING AND CONTROL OF SURFACES AND INTERFACES OF COMPOUND SEMICONDUCTORS FOR MESOSCOPIC DEVICES

2000 ◽  
Vol 07 (05n06) ◽  
pp. 583-588 ◽  
Author(s):  
HIDEKI HASEGAWA
Keyword(s):  
Fermi Level ◽  
Surface Passivation ◽  
Surface States ◽  
Compound Semiconductors ◽  
Scanning Tunneling Spectroscopy ◽  
Scanning Tunneling ◽  
Free Surfaces ◽  
Fermi Level Pinning ◽  
Interface Control ◽  
Mesoscopic Devices

Microscopic properties of free surfaces and metal–semiconductor interfaces related to successful realization of mesoscopic devices are discussed for III–V compound semiconductors, with a particular emphasis on Fermi level pinning. Surface states causing pinning are present even on freshly MBE-grown clean (001) and (110) surfaces with well-defined surface structures. Scanning tunneling spectroscopy (STS) measurement gives anomalous spectra with large conductance gaps, and this can be explained by tip-induced local charging of surface states. Pinning on free surfaces can be considerably suppressed by a surface passivation using an ultrathin MBE-grown silicon interface control layer (Si ICL). In mesoscopic scale metal–semiconductor contacts, Fermi level pinning underneath the metal contact itself is remarkably reduced with the use of the optimum in situ electrochemical metal deposition. However, Fermi level pinning on the surrounding free surfaces has large effects on current transport and capacitance properties in such contacts.

scholarly journals Fermi-Level Pinning Mechanism in MoS2 Field-Effect Transistors Developed by Thermionic Emission Theory

2020 ◽  
Vol 10 (8) ◽  
pp. 2754
Author(s):  
Yu Zhang ◽  
Xiong Chen ◽  
Hao Zhang ◽  
Xicheng Wei ◽  
Xiangfeng Guan ◽  
...  
Keyword(s):  
Fermi Level ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Thermionic Emission ◽  
Surface States ◽  
Crystal Defects ◽  
Pinning Mechanism ◽  
Fermi Level Pinning ◽  
Order Of Magnitude ◽  
Semiconductor Contacts

Molybdenum disulfide (MoS2) field-effect transistors (FETs) with four different metallic electrodes (Au,Ag,Al,Cu) of drain-source were fabricated by mechanical exfoliation and vacuum evaporation methods. The mobilities of the devices were (Au) 21.01, (Ag) 23.15, (Al) 5.35 and (Cu) 40.52 cm2/Vs, respectively. Unpredictably, the on-state currents of four devices were of the same order of magnitude with no obvious difference. For clarifying this phenomenon, we calculated the Schottky barrier height (SBH) of the four metal–semiconductor contacts by thermionic emission theory and confirmed the existence of Fermi-level pinning (FLP). We suppose the FLP may be caused by surface states of the semiconductor produced from crystal defects.

Contactless Electromodulation Characterization of Compound Semiconductor Surfaces and Device Structures

1993 ◽  
Vol 324 ◽  
Author(s):  
J.M. Woodall
Keyword(s):  
Fermi Level ◽  
Electric Fields ◽  
Growth Conditions ◽  
Compound Semiconductor ◽  
Conduction Band Edge ◽  
Semiconductor Surfaces ◽  
Air Exposure ◽  
Fermi Level Pinning ◽  
Characterization Of Properties

AbstractThis paper will review the use of contactless electromodulation methods, such as photoreflectance (PR) and contactless electroreflectance (CER), to characterize the electronic properties of compound semiconductor surfaces exposed to different growth and post-growth conditions. Also the characterization of properties critical to device performance can be evaluated. For example, using PR and CER it has been found that there is a lower density of surface hole traps than electron traps in certain as-grown MBE (001) GaAs samples and that this condition persists even after air exposure. This behaviour is in contrast to other samples, including both bulk and MBE grown (001) surfaces in which the Fermi level is pinned mid-gap for both n- and p-type structures. We also have observed that Ar+ bombardment under UHV conditions results in Fermi level pinning close to the conduction band edge and that thermal annealing restores mid-gap pinning. Finally, using PR we are able to characterize the electric fields and associated doping levels in the emitter and collector regions of heterojunction bipolar transistor structures (fabricated from III-V materials), thus demonstrating the ability to perform inprocess evaluation of important device parameters.

Effect of inside-spread surface states on Fermi level pinning

1990 ◽  
Vol 238 (1-3) ◽  
pp. 271-279 ◽  
Author(s):  
J.M Palau ◽  
M Dumas
Keyword(s):  
Fermi Level ◽  
Surface States ◽  
Fermi Level Pinning

Tomographic investigation of fermi level pinning at focused ion beam milled semiconductor surfaces

2013 ◽  
Vol 103 (26) ◽  
pp. 264104 ◽  
Author(s):  
D. Wolf ◽  
A. Lubk ◽  
A. Lenk ◽  
S. Sturm ◽  
H. Lichte
Keyword(s):  
Fermi Level ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Surfaces ◽  
Fermi Level Pinning
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