Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator

2019 ◽  
Vol 114 (19) ◽  
pp. 192105 ◽  
Author(s):  
Yu Han ◽  
Ying Xue ◽  
Kei May Lau
Keyword(s):  
Silicon On Insulator ◽  
Lateral Epitaxy

Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna
Keyword(s):  
Channel Length ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Mos Transistors ◽  
Seed Structure ◽  
Leakage Currents ◽  
Industrial Processing ◽  
Laser Recrystallization ◽  
Dynamic Performances ◽  
Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

A Study of Melting and Resolidification of Silicon-on-Insulator Structures Formed by Lateral Epitaxy

1985 ◽  
Vol 53 ◽  
Author(s):  
D A Williams ◽  
R A Mcmahon ◽  
D G Hasko ◽  
H Ahmed ◽  
G F Hopper ◽  
...  
Keyword(s):  
Cross Sections ◽  
Silicon On Insulator ◽  
One Dimensional ◽  
Wide Range ◽  
Background Temperature ◽  
Lateral Epitaxy ◽  
Polycrystalline Silicon Films ◽  
Beam Technique ◽  
Sweep Speed

ABSTRACTThe formation of silicon-on-insulator structures, by recrystallising polycrystalline silicon films with a dual electron beam technique, has been studied over a wide range of conditions. The quality of the layers has been assessed by examining cross-sections in the SEM and optical microscopy of the surface after a Secco etch. The range of line powers which gives device-worthy single crystal material becomes greater as the sweep speed increases and as the background temperature is reduced. The extent of melting into the substrate in the seed windows and below the isolating oxide was determined from the movement of an arsenic implant. The experimental results are compared to the predictions from a one dimensional model for the heat flow.

Summary Abstract: Seeded lateral epitaxy in silicon‐on‐insulator structures

1987 ◽  
Vol 5 (4) ◽  
pp. 1393-1394 ◽  
Author(s):  
T. Warabisako ◽  
T. Tokuyama ◽  
M. Tamura ◽  
M. Miyao
Keyword(s):  
Silicon On Insulator ◽  
Lateral Epitaxy

Laser-induced lateral epitaxy in fully depleted silicon-on-insulator junctions

2002 ◽  
Vol 81 (12) ◽  
pp. 2238-2240 ◽  
Author(s):  
Kevin K. Dezfulian ◽  
J. Peter Krusius ◽  
Michael O. Thompson ◽  
Somit Talwar
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Lateral Epitaxy

Seeding lateral epitaxy of silicon on insulator with improved seed and cap structure by pseudoline shaped electron beam annealing

1985 ◽  
Vol 47 (7) ◽  
pp. 696-699 ◽  
Author(s):  
K. Suguro ◽  
T. Inoue ◽  
T. Hamasaki ◽  
T. Yoshii ◽  
M. Yoshimi ◽  
...  
Keyword(s):  
Electron Beam ◽  
Silicon On Insulator ◽  
Lateral Epitaxy

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

In Situ microscopy of the anodic etching of silicon

1995 ◽  
Vol 53 ◽  
pp. 232-233
Author(s):  
Frances M. Ross ◽  
Peter C. Searson
Keyword(s):  
Composite Structures ◽  
High Surface ◽  
High Surface Area ◽  
Chemical Properties ◽  
Selective Etching ◽  
Silicon On Insulator ◽  
Second Phase ◽  
Porous Layers ◽  
New Class ◽  
Porous Semiconductors

Porous semiconductors represent a relatively new class of materials formed by the selective etching of a single or polycrystalline substrate. Although porous silicon has received considerable attention due to its novel optical properties1, porous layers can be formed in other semiconductors such as GaAs and GaP. These materials are characterised by very high surface area and by electrical, optical and chemical properties that may differ considerably from bulk. The properties depend on the pore morphology, which can be controlled by adjusting the processing conditions and the dopant concentration. A number of novel structures can be fabricated using selective etching. For example, self-supporting membranes can be made by growing pores through a wafer, films with modulated pore structure can be fabricated by varying the applied potential during growth, composite structures can be prepared by depositing a second phase into the pores and silicon-on-insulator structures can be formed by oxidising a buried porous layer. In all these applications the ability to grow nanostructures controllably is critical.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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