Laser-induced lateral epitaxy in fully depleted silicon-on-insulator junctions

2002 ◽  
Vol 81 (12) ◽  
pp. 2238-2240 ◽  
Author(s):  
Kevin K. Dezfulian ◽  
J. Peter Krusius ◽  
Michael O. Thompson ◽  
Somit Talwar
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Lateral Epitaxy

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna
Keyword(s):  
Channel Length ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Mos Transistors ◽  
Seed Structure ◽  
Leakage Currents ◽  
Industrial Processing ◽  
Laser Recrystallization ◽  
Dynamic Performances ◽  
Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors

2015 ◽  
Vol 118 (18) ◽  
pp. 184504 ◽  
Author(s):  
C. Navarro ◽  
M. Bawedin ◽  
F. Andrieu ◽  
B. Sagnes ◽  
F. Martinez ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Short Channel ◽  
Fully Depleted

Large Injection Velocities in Highly Scaled, Fully Depleted Silicon on Insulator Transistors

2021 ◽  
pp. 1-1
Author(s):  
Yu-Hung Liao ◽  
Khandker Akif Aabrar ◽  
Wriddhi Chakraborty ◽  
Wenshen Li ◽  
Suman Datta ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Large Injection

Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

2018 ◽  
Vol 86 (7) ◽  
pp. 199-206 ◽  
Author(s):  
Ömür Işıl Aydin ◽  
Judson Robert Holt ◽  
Cyrille Le Royer ◽  
Laks Vanamurthy ◽  
Thomas Feudel ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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