Drain current overshoot transient in polycrystalline silicon transistors: The effect of hole generation mechanism

2006 ◽  
Vol 99 (2) ◽  
pp. 024511 ◽  
Author(s):  
M. Exarchos ◽  
G. J. Papaioannou ◽  
D. N. Kouvatsos ◽  
A. T. Voutsas
Keyword(s):  
Polycrystalline Silicon ◽  
Drain Current ◽  
Generation Mechanism ◽  
Silicon Transistors ◽  
Hole Generation

Systematic Analysis of High-Current Effects in Flexible Polycrystalline-Silicon Transistors Fabricated on Polyimide

2017 ◽  
Vol 64 (8) ◽  
pp. 3167-3173 ◽  
Author(s):  
Bo-Wei Chen ◽  
Hsin-Lu Chen ◽  
Ting-Chang Chang ◽  
Yu-Ju Hung ◽  
Shin-Ping Huang ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
High Current ◽  
Systematic Analysis ◽  
Silicon Transistors

The effect of generation–recombination mechanisms on the transient behavior of polycrystalline silicon transistors

2005 ◽  
Vol 487 (1-2) ◽  
pp. 247-251 ◽  
Author(s):  
G.J. Papaioannou ◽  
A. Voutsas ◽  
M. Exarchos ◽  
D. Kouvatsos
Keyword(s):  
Polycrystalline Silicon ◽  
Transient Behavior ◽  
Silicon Transistors

P-channel Polycrystalline Silicon Thin Film Transistors on Steel Foil Substrates

2001 ◽  
Vol 664 ◽  
Author(s):  
Ming Wu ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Field Effect ◽  
Drain Current ◽  
Silicon Thin Film ◽  
Polysilicon Films ◽  
Source Voltage ◽  
Steel Substrates ◽  
Hydrogenated Amorphous

ABSTRACTWe fabricated self-aligned polycrystalline silicon (polysilicon) thin film transistors on flexible steel substrates. The polysilicon was formed by furnace crystallization of hydrogenated amorphous silicon at 950°C/20sec or 750°C/2min. The TFTs made from these polysilicon films have hole field effect mobilities in the linear regime of 22 cm2·V−1s−1 (950°C) and 14 cm2·V−1s−1 (750°C). The OFF current at 10 V drain-source voltage is 10−10A and the drain current ON/OFF ratio is ∼106.

scholarly journals Solution-based polycrystalline silicon transistors produced on a paper substrate

2017 ◽  
Vol 1 (1) ◽  
Author(s):  
Miki Trifunovic ◽  
Paolo Maria Sberna ◽  
Tatsuya Shimoda ◽  
Ryoichi Ishihara
Keyword(s):  
Polycrystalline Silicon ◽  
Paper Substrate ◽  
Silicon Transistors

Surface-Potential-Based Drain Current Model for Polycrystalline Silicon Thin-Film Transistors

2008 ◽  
Vol 47 (10) ◽  
pp. 7798-7802 ◽  
Author(s):  
Hiroshi Tsuji ◽  
Tsuyoshi Kuzuoka ◽  
Yuji Kishida ◽  
Yoshiyuki Shimizu ◽  
Masaharu Kirihara ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface Potential ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Current Model ◽  
Drain Current ◽  
Silicon Thin Film

Dimension scaling of low frequency noise in the drain current of polycrystalline silicon thin-film transistors

1999 ◽  
Vol 86 (12) ◽  
pp. 7083-7086 ◽  
Author(s):  
C. T. Angelis ◽  
C. A. Dimitriadis ◽  
F. V. Farmakis ◽  
J. Brini ◽  
G. Kamarinos ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Low Frequency ◽  
Drain Current ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Silicon Thin Film

Dielectric Effects in Laser-Crystallised Polycrystalline Silicon Thin Film Transistors

1995 ◽  
Vol 377 ◽  
Author(s):  
G. H. Masterton ◽  
R. A. G. Gibson ◽  
M. Hack
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Gate Dielectric ◽  
Drain Current ◽  
Generation Process ◽  
Gate Bias ◽  
Silicon Thin Film ◽  
Transient Behaviour ◽  
Current Decay

ABSTRACTWe present experimental results on the transient response of the source-drain current of laser crystallised polycrystalline silicon (poly-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate electrode. This work follows on from similar measurements performed on amorphous silicon (a-Si) TFTs. Results showed a definite change in transient behaviour dependent on the magnitude of the gate bias. At a gate voltage of 5V there was an initial decay then a marked increase in the source-drain current beyond 1000 seconds. This variation of transient behaviour with gate bias was not seen in the a-Si case. For poly-Si the transient behaviour could not be split into different regimes in time (beyond the carrier transit time) whereas for a-Si TFTs the source-drain current showed a logarithmic decay at room temperature up to 100 seconds followed by a power law decay beyond 100 seconds. Our results indicate perhaps that only one mechanism exists for the observed transient decay of current, unlike the a-Si case. Measurements carried out at elevated temperature showed the current decay was independent of temperature indicating that the transient decay may be caused by charge injection via a tunnelling process into interface states, gate dielectric or passivation dielectric. Finally by carrying out measurements on TFTs after moderate positive voltage stressing and on TFTs with specially fabricated gate and passivation dielectrics it has been established that the transient decay is dielectric related and not a defect generation process.

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