Dielectric Effects in Laser-Crystallised Polycrystalline Silicon Thin Film Transistors

1995 ◽  
Vol 377 ◽  
Author(s):  
G. H. Masterton ◽  
R. A. G. Gibson ◽  
M. Hack

ABSTRACTWe present experimental results on the transient response of the source-drain current of laser crystallised polycrystalline silicon (poly-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate electrode. This work follows on from similar measurements performed on amorphous silicon (a-Si) TFTs. Results showed a definite change in transient behaviour dependent on the magnitude of the gate bias. At a gate voltage of 5V there was an initial decay then a marked increase in the source-drain current beyond 1000 seconds. This variation of transient behaviour with gate bias was not seen in the a-Si case. For poly-Si the transient behaviour could not be split into different regimes in time (beyond the carrier transit time) whereas for a-Si TFTs the source-drain current showed a logarithmic decay at room temperature up to 100 seconds followed by a power law decay beyond 100 seconds. Our results indicate perhaps that only one mechanism exists for the observed transient decay of current, unlike the a-Si case. Measurements carried out at elevated temperature showed the current decay was independent of temperature indicating that the transient decay may be caused by charge injection via a tunnelling process into interface states, gate dielectric or passivation dielectric. Finally by carrying out measurements on TFTs after moderate positive voltage stressing and on TFTs with specially fabricated gate and passivation dielectrics it has been established that the transient decay is dielectric related and not a defect generation process.

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  

2001 ◽  
Vol 664 ◽  
Author(s):  
Ming Wu ◽  
Sigurd Wagner

ABSTRACTWe fabricated self-aligned polycrystalline silicon (polysilicon) thin film transistors on flexible steel substrates. The polysilicon was formed by furnace crystallization of hydrogenated amorphous silicon at 950°C/20sec or 750°C/2min. The TFTs made from these polysilicon films have hole field effect mobilities in the linear regime of 22 cm2·V−1s−1 (950°C) and 14 cm2·V−1s−1 (750°C). The OFF current at 10 V drain-source voltage is 10−10A and the drain current ON/OFF ratio is ∼106.


2011 ◽  
Vol 98 (12) ◽  
pp. 122101 ◽  
Author(s):  
Chia-Sheng Lin ◽  
Ying-Chung Chen ◽  
Ting-Chang Chang ◽  
Fu-Yen Jian ◽  
Hung-Wei Li ◽  
...  

2008 ◽  
Vol 47 (10) ◽  
pp. 7798-7802 ◽  
Author(s):  
Hiroshi Tsuji ◽  
Tsuyoshi Kuzuoka ◽  
Yuji Kishida ◽  
Yoshiyuki Shimizu ◽  
Masaharu Kirihara ◽  
...  

1993 ◽  
Vol 297 ◽  
Author(s):  
M. Hack ◽  
R. Weisfield ◽  
M.F. Willums ◽  
G.H. Masterton ◽  
P.G. Lecomber

In this paper we present experimental and simulation results of the transient response of amorphous silicon (a-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate. In general three regimes are observed by plotting drain current versus the logarithm of time. At times longer than the carrier transit time and extending up to 1 - 100 msecs, the current rapidly decreases due to trap filling, after which it then slowly decays up until defects are created in the silicon channel when it then finally decays more rapidly again. Our simulation results are in good agreement with the data for the short time trap filling regime, as a function of both gate bias and stress condition. Measurements at elevated temperatures show that the middle slow decay regime is caused by charge injection into interface states or the gate dielectric. Finally we also demonstrate that this slow decay regime does not occur in nin diodes, confirming that it is not caused by defect generation in the a-Si, and is instead related to the presence of the dielectric in a TFT.


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