Reduced charge trapping in GaN MIS using gate oxide deposition technique

2009 ◽  
Vol 45 (10) ◽  
pp. 527
Author(s):  
T. Sreenidhi ◽  
K. Baskar ◽  
A. DasGupta ◽  
N. DasGupta
Keyword(s):  
Charge Trapping ◽  
Gate Oxide ◽  
Deposition Technique ◽  
Oxide Deposition

Improvement of Gate Oxide Integrity in Low Temperature Poly Silicon TFT

2003 ◽  
Vol 762 ◽  
Author(s):  
Seok-Woo Lee ◽  
Dae Hyun Nam ◽  
Jin Mo Yoon ◽  
Hyun Sik Seo ◽  
Kyoung Moon Lim ◽  
...  
Keyword(s):  
Elevated Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Oxide Deposition ◽  
Gate Oxide Integrity

AbstractThe electrical characteristics of SiH4-based PECVD gate oxide have been investigated with respect to gate oxide integrity (GOI) and its reliability. It was found that the GOI of poly-Si TFT integrated on glass substrate strongly depended on the charge trapping and deep level interface states generation under Fowler-Nordheim stress (FNS). By applying elevated temperature postanneal without vacuum break after the gate oxide deposition, highly reliable gate oxide was obtained. Under FNS, ID-VG curve showed severe shift and degradation of subthreshold slope, which were reduced by adopting post-annealed gate oxide. Besides, the TFT with post-annealed gate oxide showed around 10 times higher charge to breakdown than that of as-deposited gate oxide. Charge to breakdown of MOS capacitors were also studied. By applying post-annealed gate oxide, charge to breakdown drastically improved, which could be explained by reduced charge trapping under FNS.

scholarly journals Charge trapping and retention behaviors of Ge nanocrystals distributed in the gate oxide near the gate synthesized by low-energy ion implantation

2007 ◽  
Vol 101 (12) ◽  
pp. 124313 ◽  
Author(s):  
M. Yang ◽  
T. P. Chen ◽  
J. I. Wong ◽  
C. Y. Ng ◽  
Y. Liu ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Low Energy ◽  
Ge Nanocrystals

Tunneling Effects in NH3 Annealed 4H-SiC Trench MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 652-658
Author(s):  
Judith Berens ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Effective Activation Energy ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Performance ◽  
Trap Level ◽  
Effective Activation ◽  
Oxide Reliability ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Mos Structures

The interface between the gate oxide and silicon carbide (SiC) has a strong influence on the performance and reliability of SiC MOSFETs and thus, requires special attention. In order to reduce charge trapping at the interface, post oxidation anneals (POAs) are conventionally applied. However, these anneals do not only influence the device performance, such as mobility and on-resistance, but also the gate oxide reliability. We study the oxide tunneling mechanisms of NH3 annealed 4H-SiC trench MOSFET test structures and compare them to devices which received a NO POA. We show that 3 different mechanisms, namely trap assisted tunneling (TAT), Fowler-Nordheim (FN) tunneling and charge trapping are found for NH3 annealed MOS structures whereas only FN-tunneling is observed in NO annealed devices.The tunneling barrier suggest a trap level with an effective activation energy of 382 meV to enable TAT.

Compatibility of POCl3 Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 565-570
Author(s):  
Tomokatsu Watanabe ◽  
Munetaka Noguchi ◽  
Shingo Tomohisa ◽  
Naruhisa Miura
Keyword(s):  
Thermal Treatment ◽  
Low Temperature ◽  
Negative Charge ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Post Processing ◽  
Production Lines ◽  
Channel Mobility ◽  
Device Operation

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

S-Passivation of the Ge Gate Stack Using (NH4)2S

2012 ◽  
Vol 187 ◽  
pp. 23-26 ◽  
Author(s):  
Sonja Sioncke ◽  
Claudia Fleischmann ◽  
Dennis Lin ◽  
Evi Vrancken ◽  
Matty Caymax ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Gate Stack ◽  
Process Flow ◽  
Oxide Deposition

The last decennia, a lot of effort has been made to introduce new channel materials in a Si process flow. High mobility materials such as Ge need a good gate stack passivation in order to ensure optimal MOSFET operation. Several routes for passivating the Ge gate stack have been explored in the last years. We present here the S-passivation of the Ge gate stack: (NH4)2S is used to create a S-terminated Ge surface. In this paper the S-treatment is discussed. The S-terminated Ge surface is not chemically passive but can still react with air. After gate oxide deposition, the Ge-S bonds are preserved and an adequate passivation is found for pMOS operation.

Dependence of gate oxide breakdown on initial charge trapping under Fowler-Nordheim injection

1998 ◽  
Vol 38 (6-8) ◽  
pp. 1091-1096
Author(s):  
A. Martin ◽  
R. Duane ◽  
P. O'Sullivan ◽  
A. Mathewson
Keyword(s):  
Charge Trapping ◽  
Gate Oxide ◽  
Oxide Breakdown ◽  
Initial Charge

The Roles of Several E′ Variants in Thermal Gate Oxide Reliability

1994 ◽  
Vol 338 ◽  
Author(s):  
John F. Conley ◽  
P.M. Lenahan ◽  
H.L. Evans ◽  
R.K. Lowry ◽  
T.J. Morthorst
Keyword(s):  
Thin Film ◽  
Electron Spin Resonance ◽  
Electron Spin ◽  
Vacuum Ultraviolet ◽  
Charge Injection ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Oxide Reliability ◽  
Spin Resonance ◽  
Thermally Grown

ABSTRACTWe combine electron spin resonance measurements with vacuum ultraviolet, ultraviolet, and corona bias charge injection schemes to examine the properties and charge trapping roles of three E′ variants in conventionally processed thermally grown thin film SiO2 on Si.

Study of gate oxide leakage and charge trapping in ZMR and SIMOX SOI MOSFETs

1988 ◽  
Vol 9 (5) ◽  
pp. 235-237 ◽  
Author(s):  
C.-T. Lee ◽  
J.A. Burns
Keyword(s):  
Charge Trapping ◽  
Gate Oxide ◽  
Simox Soi
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