Effect of ultraviolet curing wavelength on low-k dielectric material properties and plasma damage resistance

Premysl Marsik; Adam M. Urbanowicz; Patrick Verdonck; David De Roest; Hessel Sprey; Mikhail R. Baklanov

doi:10.1016/j.tsf.2011.01.339

Ultra Low-k Materials Based on Self-Assembled Organic Polymers

MRS Proceedings ◽

10.1557/opl.2011.1200 ◽

2011 ◽

Vol 1335 ◽

Author(s):

M. Pantouvaki ◽

L. Zhao ◽

C. Huffman ◽

K. Vanstreels ◽

I. Ciofi ◽

...

Keyword(s):

Pore Size ◽

Material Properties ◽

Open Porosity ◽

Dielectric Breakdown ◽

Organic Polymers ◽

Plasma Damage ◽

Small Pore Size ◽

Small Pore ◽

Lower Porosity ◽

Low K

ABSTRACTThe material properties of two ultra low-k organic polymers are characterized for copper interconnect integration. The k-values are 2.2-2.3 for both. Compared to OSG materials of similar k-values, these polymers have lower porosity and smaller pore size, achieved using selfassembled chemistry. Both materials demonstrate excellent resistance to plasma damage: no water uptake was detected after exposure to selected etching plasmas. This characteristic, combined with the small pore size and low porosity, results in the successful integration of the organic low-ks in 80 nm spacing with no significant increase in the integrated k-values.It is found that higher open porosity in polymer A is accompanied by higher leakage current, which is not however linked to lower dielectric breakdown lifetimes.

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Porous ultra low k deposited by PECVD: From deposition to material properties

Surface and Coatings Technology ◽

10.1016/j.surfcoat.2007.04.105 ◽

2007 ◽

Vol 201 (22-23) ◽

pp. 9248-9251 ◽

Cited By ~ 23

Author(s):

V. Jousseaume ◽

L. Favennec ◽

A. Zenasni ◽

O. Gourhant

Keyword(s):

Material Properties ◽

Low K

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The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

MRS Proceedings ◽

10.1557/proc-565-203 ◽

1999 ◽

Vol 565 ◽

Cited By ~ 1

Author(s):

N. Ariel ◽

M. Eizenberg ◽

E. Y. Tzou

Keyword(s):

Amorphous Carbon ◽

Nuclear Reactions ◽

Dielectric Material ◽

Copper Metallization ◽

Limiting Factor ◽

Adhesion Promoter ◽

Adhesion Promotion ◽

High Resolution Tem ◽

Rc Delay ◽

Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

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Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

MRS Proceedings ◽

10.1557/proc-716-b7.20 ◽

2002 ◽

Vol 716 ◽

Cited By ~ 4

Author(s):

Ilanit Fisher ◽

Wayne D. Kaplan ◽

Moshe Eizenberg ◽

Michael Nault ◽

Timothy Weidman

Keyword(s):

Integrated Circuits ◽

Dielectric Material ◽

Hydrogen Plasma ◽

Porous Silica ◽

Film Deposition ◽

Copper Metallization ◽

High Porosity ◽

Tem Analysis ◽

Chip Technology ◽

Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

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Advanced Die Saw Technology for WLCSP Reliability Enhancement

International Symposium on Microelectronics ◽

10.4071/2380-4505-2019.1.000323 ◽

2019 ◽

Vol 2019 (1) ◽

pp. 000323-000326

Author(s):

Ching Chia Chen ◽

Yu-Po Wang ◽

Jensen Tsai ◽

Hsin Long Chen

Keyword(s):

Plasma Etching ◽

Dielectric Material ◽

Side Wall ◽

Bending Test ◽

Process Time ◽

Portable Devices ◽

Coating Materials ◽

Reliability Enhancement ◽

Surrounding Areas ◽

Low K

Abstract As consumer and portable devices get thinner and more functionality. Chips which are made by less than 28 nm node wafer with extreme Low-k (ELK) inter metal dielectric material is a trend in order to contain more transistors and to lower power consumption. However, side wall crack (SWC) for WLCSP is one of the major challenges since ELK layer getting brittle. Laser grooving is applied to remove metal before blade saw, but the high temperature during laser grooving usually easily generates HAZ (heat-affected zone) which can induce stress concentration and lower chip strength. The laser ablation also leaves metal-silicon residue (or recast) from the re-deposition of silicon to the groove and surrounding areas. Therefore, SWC (sidewall crack) is a huge potential risk waiting to happen after pick and place, during shipment and during SMT process. In the industry, HAZ size and SWC rate could be reduced by adjusting process parameters, or by exploring new alternatives to eliminate HAZ and silicon recast is one of driving factors of this paper. In this study, plasma etching was applied as surface treatment on the scribe line after laser grooving process with ELK wafer. Plasma could etch HAZ and recast area and expected to increase chip strength and reduce SWC rate. Plasma applied with various process time and power, and different types of mask coating materials were studied. Different plasma gases and effectiveness will be discussed. Conventional blade dicing process will be compared to different plasma etching conditions for mechanical properties of die using 3-point bending test to check die strength, and SEM and OM to verify quality of sidewall of the die. Finally drop test was performed to confirm the reliability enhancement.

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Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

Journal of Microelectronics and Electronic Packaging ◽

10.4071/1551-4897-6.1.59 ◽

2009 ◽

Vol 6 (1) ◽

pp. 59-65

Author(s):

Karan Kacker ◽

Suresh K. Sitaraman

Keyword(s):

Failure Analysis ◽

Dielectric Material ◽

Organic Substrate ◽

Wafer Level ◽

Free Standing ◽

Fine Pitch ◽

Cross Section Area ◽

Interconnect Reliability ◽

Compliant Interconnect ◽

Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

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Proposal of New Precursors for Plasma-Enhanced Chemical Vapor Deposition of SiOCH Low-kFilms with Plasma Damage Resistance

Japanese Journal of Applied Physics ◽

10.1143/jjap.49.05ff03 ◽

2010 ◽

Vol 49 (5) ◽

pp. 05FF03 ◽

Cited By ~ 5

Author(s):

Yoshi Ohashi ◽

Nobuo Tajima ◽

Yonghua Xu ◽

Takeshi Kada ◽

Shuji Nagano ◽

...

Keyword(s):

Chemical Vapor Deposition ◽

Vapor Deposition ◽

Chemical Vapor ◽

Plasma Damage ◽

Damage Resistance

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Changes of UV Optical Properties of Plasma Damaged Low-k Dielectrics for Sidewall Damage Scatterometry

MRS Proceedings ◽

10.1557/proc-1079-n07-04 ◽

2008 ◽

Vol 1079 ◽

Cited By ~ 4

Author(s):

Premysl Marsik ◽

Adam Urbanowicz ◽

Klara Vinokur ◽

Yoel Cohen ◽

Mikhail R Baklanov

Keyword(s):

Thin Film ◽

Optical Properties ◽

Optical Model ◽

Concentration Profiles ◽

Atomic Concentration ◽

Plasma Damage ◽

Tof Sims ◽

Plasma Treatments ◽

Water Based ◽

Low K

ABSTRACTPorous low-k dielectrics were studied to determine the changes of optical properties after various plasma treatments for development of scatterometry technique for evaluation of the trench/via sidewall plasma damage. The SiCOH porogen based low-k films were prepared by PE-CVD. The deposited and UV-cured low-k films have been damaged by striping O2Cl2, O2, NH3 and H2N2 based plasmas and CF4/CH2F2/Ar etching plasma. Blanket wafers were studied in this work for the simplicity of thin film optical model. The optical properties of the damaged low-k dielectrics are evaluated the using various angle spectroscopic ellipsometry in range from 2 to 9 eV. Multilayer optical model is applied to fit the measured quantities and the validity is supported by other techniques. The atomic concentration profiles of Si, C, O and H were stated by TOF-SIMS and changes in overall chemical composition were derived from FTIR. Toluene and water based ellipsometric porosimetry is involved to examine the porosity, pore interconnectivity and internal hydrophilicity.

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