scholarly journals The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology

2016 ◽  
Vol 67 ◽  
pp. 74-81 ◽  
Author(s):  
Basel Halak ◽  
Vasileios Tenentes ◽  
Daniele Rossi
Keyword(s):  
Cmos Technology ◽  
Nano Scale ◽  
Level Shifters ◽  
The Impact

scholarly journals The Impact of Microelectronics on High Energy Physics Innovation: The Role of 65 nm CMOS Technology on New Generation Particle Detectors

2021 ◽  
Vol 9 ◽  
Author(s):  
N. Demaria
Keyword(s):  
Particle Physics ◽  
High Energy Physics ◽  
Hadron Collider ◽  
Cmos Technology ◽  
High Energy ◽  
Main Role ◽  
Noise Power ◽  
Recent Developments ◽  
The Impact ◽  
Energy Physics

The High Luminosity Large Hadron Collider (HL-LHC) at CERN will constitute a new frontier for the particle physics after the year 2027. Experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sensors and electronics will have a main role in this. This paper describes the recent developments in 65 nm CMOS technology for readout ASIC chips in future High Energy Physics (HEP) experiments. These allow unprecedented performance in terms of speed, noise, power consumption and granularity of the tracking detectors.

scholarly journals A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950110 ◽  
Author(s):  
K. Hayatleh ◽  
S. Zourob ◽  
R. Nagulapalli ◽  
S. Barker ◽  
N. Yassine ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
High Performance ◽  
Impedance Measurement ◽  
Cmos Technology ◽  
Skin Impedance ◽  
Instrumentation Amplifier ◽  
Measurement Circuit ◽  
Silicon Area ◽  
The Impact ◽  
Mode Interference

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.

scholarly journals Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4663
Author(s):  
Rafel Perello-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Fluid Flow ◽  
Gas Sensing ◽  
Low Cost ◽  
Cmos Technology ◽  
Monolithically Integrated ◽  
Impact Reduction ◽  
Mems Resonators ◽  
Cmos Mems ◽  
Outstanding Result ◽  
The Impact

Based on experimental data, this paper thoroughly investigates the impact of a gas fluid flow on the behavior of a MEMS resonator specifically oriented to gas sensing. It is demonstrated that the gas stream action itself modifies the device resonance frequency in a way that depends on the resonator clamp shape with a corresponding non-negligible impact on the gravimetric sensor resolution. Results indicate that such an effect must be accounted when designing MEMS resonators with potential applications in the detection of volatile organic compounds (VOCs). In addition, the impact of thermal perturbations was also investigated. Two types of four-anchored CMOS-MEMS plate resonators were designed and fabricated: one with straight anchors, while the other was sustained through folded flexure clamps. The mechanical structures were monolithically integrated together with an embedded readout amplifier to operate as a self-sustained fully integrated oscillator on a commercial CMOS technology, featuring low-cost batch production and easy integration. The folded flexure anchor resonator provided a flow impact reduction of 5× compared to the straight anchor resonator, while the temperature sensitivity was enhanced to −115 ppm/°C, an outstanding result compared to the −2403 ppm/°C measured for the straight anchored structure.

scholarly journals Theory, Analysis and Implementation of an On-Line BIST Technique

VLSI Design ◽  
1993 ◽  
Vol 1 (1) ◽  
pp. 9-22 ◽  
Author(s):  
Rajiv Sharma ◽  
Kewal K. Saluja
Keyword(s):  
Cmos Technology ◽  
Normal Operation ◽  
Theory Analysis ◽  
Chip Area ◽  
Intermittent Faults ◽  
Simulation Techniques ◽  
System Maintenance ◽  
On Line ◽  
Line Test ◽  
The Impact

A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with their normal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce the overall area overhead is introduced. The method was implemented in the design of an ALU with on-line test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU.Following the description of the BICST technique, measures for evaluating the performance of the BICST technique are defined. Methods for the computation of the performance measures using analytical and simulation techniques are discussed and results of these methods are reported. Methods for detecting intermittent faults and for computing the transient fault coverage using BICST are also described. The impact of BICST on the system diagnostics and system maintenance is discussed.

Considerations and Optimization of Measurement Accuracy of Capacitance in Nano-Scale CMOS Technology

2012 ◽  
Vol 4 (9) ◽  
pp. 924-929 ◽  
Author(s):  
Si Han Cao ◽  
Xiao Peng Yu ◽  
Yun Pan ◽  
Zheng Shi ◽  
Chang Hui Hu
Keyword(s):  
Measurement Accuracy ◽  
Cmos Technology ◽  
Nano Scale

Impact of temperature and breakdown statistics on reliability predictions for ultrathin oxides

1999 ◽  
Vol 592 ◽  
Author(s):  
G. Groeseneken ◽  
R. Degraeve ◽  
B. Kaczer ◽  
H.E. Maes
Keyword(s):  
Oxide Thickness ◽  
Cmos Technology ◽  
Percolation Model ◽  
Strong Increase ◽  
Combined Effects ◽  
Technology Scaling ◽  
Test Methodology ◽  
Oxide Reliability ◽  
Ultrathin Oxides ◽  
The Impact

ABSTRACTThis paper discusses the evolution in the degradation and breakdown behaviour of ultra-thin oxides when scaling the oxide thickness into the sub-4 nm range for future CMOS technology generations. It will be shown that changes in the breakdown statistics, which can be explained by a percolation model for breakdown, lead to an increased area dependence of the time-tobreakdown. This has to be taken into account when predicting the oxide reliability. Also the impact of the test methodology, the relevance of a so-called polarity gap in the charge-tobreakdown and its consequences for reliability testing, are highlighted. Moreover, a strong increase in the temperature dependence of breakdown, especially for sub-3 nm oxides, is demonstrated and the impact of temperature on trap generation and critical trap density at breakdown is discussed. Finally it is shown that the combined effects of all these phenomena might lead to oxide reliability becoming a potential showstopper for further technology scaling.

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