ulsi fabrication
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2004 ◽  
Vol 812 ◽  
Author(s):  
L. Wang ◽  
J. Liu ◽  
W.D. Wang ◽  
D.Z. Chi ◽  
D. W. Gidley ◽  
...  

AbstractThe application of porous low-k interlayer dielectrics is needed for reducing the parasitical capacitance, especially at 65-nm node and beyond. The understanding of process-induced modifications to material properties is crucial for a successful integration of these low-k dielectrics. The dry etching processes of porous low-k materials are important modules in ULSI fabrication. In this study, the interaction between MSQ-based JSR LKD-5109 films (shown by PALS to have interconnected 2.8 nm size pores) with CF4/O2 plasma has been investigated. Various ratios of O2 content were designed to characterize its effects on the etch rate, formation of polymerization layer, and properties of the LKD-5109 film. Composition analysis was conducted by SIMS and FTIR. Moisture absorption and fluorine diffusion into low-k films after etch process are observed, along with carbon depletion near the surface region. The influence of etching chemistries on the morphological characteristics of thin Ta barrier layers (8-nm in thickness) deposited on etched low-k films were further investigated by SEM, and it is found that oxygen concentration has significant influences on the morphological characteristics of thin Ta barriers.


2003 ◽  
Vol 430 (1-2) ◽  
pp. 265-269 ◽  
Author(s):  
Akira Izumi ◽  
Tsubasa Miki ◽  
Hideki Matsumura
Keyword(s):  

1997 ◽  
Author(s):  
Ryuji Takenouchi ◽  
Hidetoshi Ohnuma ◽  
Isao Ashida ◽  
Satoru Nozawa

1997 ◽  
Vol 470 ◽  
Author(s):  
Yukio Takáno ◽  
Katsunori Kakumoto ◽  
Tomoya Funakoshi

ABSTRACTRTP will be replaced with some of the conventional thermal processing employed in ULSI fabrication lines in near future. We show at first the device characteristics demanded for next generation DRAM which is a typical example of ULSIs and some issues to satisfy the demands. Next we show some candidates for RTP in the ULSI processes and discuss difference between RTP and the conventional thermal processes. We think one of the largest difference is the quenching Si wafers after short time annealing and by the quenching the deep levels due to fast diffusing atoms and point defects in Si are introduced. Experimental results of N2 and Cu related deep levels are shown as the examples of the deep levels induced by the quenching in Si. Finally, we propose the gettering method for them in RTP.


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