17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.
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Data compression for system-on-chip testing using ATE

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173513 ◽

2003 ◽

Cited By ~ 3

Author(s):

F. Karimi ◽

W. Meleis ◽

Z. Navabi ◽

F. Lombardi

Keyword(s):

Data Compression ◽

System On Chip ◽

Chip Testing ◽

On Chip

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Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173535 ◽

2003 ◽

Cited By ~ 2

Author(s):

S.S. Sabade ◽

D.M.H. Walker

Keyword(s):

Data Analysis ◽

Current Ratio

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A new functional fault model for FPGA application-oriented testing

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173534 ◽

2003 ◽

Cited By ~ 12

Author(s):

M. Rebaudengo ◽

M.S. Reorda ◽

M. Violante

Keyword(s):

Fault Model

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Testing layered interconnection networks

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173526 ◽

2003 ◽

Author(s):

F. Lombardi ◽

N. Park

Keyword(s):

Interconnection Networks

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On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173517 ◽

2003 ◽

Cited By ~ 3

Author(s):

C. Metra ◽

S. Di Francescantonio ◽

G. Marrale

Keyword(s):

Transient Faults ◽

On Line ◽

Functional Blocks

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Adaptive test scheduling in SoC's by dynamic partitioning

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173530 ◽

2003 ◽

Cited By ~ 7

Author(s):

Dan Zhao ◽

S. Upadhyaya

Keyword(s):

Test Scheduling ◽

Adaptive Test ◽

Dynamic Partitioning

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Neural networks-based parametric testing of analog IC

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173538 ◽

2003 ◽

Cited By ~ 3

Author(s):

V. Stopjakova ◽

D. Micusik ◽

L. Benuskova ◽

M. Margala

Keyword(s):

Neural Networks ◽

Analog Ic ◽

Parametric Testing

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New methods for evaluating the impact of single event transients in VDSM ICs

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173506 ◽

2003 ◽

Cited By ~ 9

Author(s):

D. Alexandrescu ◽

L. Anghel ◽

M. Nicolaidis

Keyword(s):

Single Event ◽

New Methods ◽

Single Event Transients ◽

The Impact

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Inserting test points to control peak power during scan testing

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173510 ◽

2003 ◽

Cited By ~ 27

Author(s):

R. Sankaralingam ◽

N.A. Touba

Keyword(s):

Peak Power ◽

Scan Testing ◽

Test Points

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Injecting bit flip faults by means of a purely software approach: a case studied

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173507 ◽

2003 ◽

Cited By ~ 6

Author(s):

R. Velazco ◽

A. Corominas ◽

P. Ferreyra

Keyword(s):

Bit Flip

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17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Data compression for system-on-chip testing using ATE

Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis

A new functional fault model for FPGA application-oriented testing

Testing layered interconnection networks

On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits

Adaptive test scheduling in SoC's by dynamic partitioning

Neural networks-based parametric testing of analog IC

New methods for evaluating the impact of single event transients in VDSM ICs

Inserting test points to control peak power during scan testing

Injecting bit flip faults by means of a purely software approach: a case studied

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.
Latest Publications