Injecting bit flip faults by means of a purely software approach: a case studied

2003 ◽  
Author(s):  
R. Velazco ◽  
A. Corominas ◽  
P. Ferreyra
Keyword(s):  
Bit Flip

Memory Implementation using Multi Bit Flip-Flop

2015 ◽  
Vol 5 (2) ◽  
pp. 34-39
Author(s):  
Palagani Yellappa ◽  
◽  
Mareddi Bharathkumar ◽  
Shaik Shabana Azmi ◽  
◽  
...  
Keyword(s):  
Flip Flop ◽  
Bit Flip

scholarly journals A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

2019 ◽  
Vol 9 (22) ◽  
pp. 4733
Author(s):  
Cuiping Shao ◽  
Huiyun Li ◽  
Zheng Wang ◽  
Jiayan Fang
Keyword(s):  
Image Processing ◽  
Principal Component Analysis ◽  
Principal Component ◽  
Error Resilience ◽  
Component Analysis ◽  
Cmos Technology ◽  
Error Correcting Codes ◽  
Memory Storage ◽  
Protection Scheme ◽  
Bit Flip

Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On the other hands, state-of-the-art applications such as image processing and machine learning loosen the requirement on the levels of data protection, which result in dedicated techniques of approximated fault tolerance. In this work, we introduce a novel error protection scheme for memory, based on feature extraction through Principal Component Analysis and the modular-wise technique to segment the data before PCA. The extracted features can be protected by replacing the fault vector with the averaged confinement vectors. This approach confines the errors with either single or multi-bit flips for generic data blocks, whilst achieving significant savings on execution time and memory usage compared to traditional ECC techniques. Experimental results of image processing demonstrate that the proposed technique results in a reconstructed image with PSNR over 30 dB, while robust against both single bit and multiple bit flip errors, with reduced memory storage to just 22.4% compared to the conventional ECC-based technique.

scholarly journals Online bit flip detection for in-memory B-trees on unreliable hardware

2014 ◽  
Author(s):  
Till Kolditz ◽  
Thomas Kissinger ◽  
Benjamin Schlegel ◽  
Dirk Habich ◽  
Wolfgang Lehner
Keyword(s):  
B Trees ◽  
Bit Flip
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