2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
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9781479986064

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Using value similarity of registers for soft error mitigation

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315142 ◽

2015 ◽

Cited By ~ 2

Author(s):

Abdulaziz Eker ◽

Oguz Ergin

Keyword(s):

Soft Error ◽

Value Similarity ◽

Error Mitigation ◽

Soft Error Mitigation

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Reducing the performance overhead of resilient CMPs with substitutable resources

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315161 ◽

2015 ◽

Author(s):

A. Malek ◽

S. Tzilis ◽

D.A. Khan ◽

I. Sourdis ◽

G. Smaragdos ◽

...

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Piecewise-functional broadside tests based on intersections of reachable states

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315150 ◽

2015 ◽

Cited By ~ 1

Author(s):

Irith Pomeranz

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RotR: Rotational redundant task mapping for fail-operational MPSoCs

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315130 ◽

2015 ◽

Cited By ~ 3

Author(s):

Badrun Nahar ◽

Brett H. Meyer

Keyword(s):

Task Mapping

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A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315164 ◽

2015 ◽

Cited By ~ 22

Author(s):

Felipe Rosa ◽

Fernanda Kastensmidt ◽

Ricardo Reis ◽

Luciano Ost

Keyword(s):

Fault Injection ◽

Soft Error ◽

Many Core

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Asymmetric ECC organization in 3D-memory via spare column utilization

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315128 ◽

2015 ◽

Cited By ~ 1

Author(s):

Hyunseung Han ◽

Joon-Sung Yang

Keyword(s):

3D Memory

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Scan attack on Elliptic Curve Cryptosystem

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315146 ◽

2015 ◽

Cited By ~ 2

Author(s):

Sk Subidh Ali ◽

Ozgur Sinanoglu

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptosystem

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A configurable board-level adaptive incremental diagnosis technique based on decision trees

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315167 ◽

2015 ◽

Author(s):

Cristiana Bolchini ◽

Luca Cassano

Keyword(s):

Decision Trees ◽

Board Level ◽

Diagnosis Technique

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Chip-level anti-reverse engineering using transformable interconnects

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315145 ◽

2015 ◽

Cited By ~ 12

Author(s):

Shuai Chen ◽

Junlin Chen ◽

Domenic Forte ◽

Jia Di ◽

Mark Tehranipoor ◽

...

Keyword(s):

Reverse Engineering

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A BIST approach for counterfeit circuit detection based on NBTI degradation

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2015.7315148 ◽

2015 ◽

Cited By ~ 2

Author(s):

Puneet Ramesh Savanur ◽

Phaninder Alladi ◽

Spyros Tragoudas

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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Using value similarity of registers for soft error mitigation

Reducing the performance overhead of resilient CMPs with substitutable resources

Piecewise-functional broadside tests based on intersections of reachable states

RotR: Rotational redundant task mapping for fail-operational MPSoCs

A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability

Asymmetric ECC organization in 3D-memory via spare column utilization

Scan attack on Elliptic Curve Cryptosystem

A configurable board-level adaptive incremental diagnosis technique based on decision trees

Chip-level anti-reverse engineering using transformable interconnects

A BIST approach for counterfeit circuit detection based on NBTI degradation

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
Latest Publications