A Novel Two-Stage Design Framework for Two-Dimensional Spatial Packing of Interconnected Components

Packing and routing separately are each challenging NP-hard problems. Therefore, solving the coupled packing and routing problem simultaneously will require disruptive methods to better address pressing-related challenges, such as system volume reduction, interconnect length reduction, ensuring non-intersection, and physics (thermal, hydraulic, or electromagnetic) considerations. Here we present a novel two-stage sequential design framework to perform simultaneous physics-based packing and routing optimization. Stage 1 generates interference-free initial layouts that are fed to stage 2 as starting points to perform continuous physics-based optimization. Three distinct strategies for stage 1 have been introduced recently, (1) the force-directed layout method (FDLM), (2) an extension of the shortest path algorithms (SPAs), and (3) a unique geometric topology (UGT) generation algorithm. In stage 2, a gradient-based topology optimization method is used to simultaneously optimize both component locations and interconnect routing paths. In addition to geometric considerations, this method supports optimization based on system behavior by including physics-based objectives and constraints. The proposed framework is demonstrated using three case studies. First, the layout generation methods developed for stage 1 are compared with respect to system performance metrics obtained from stage 2. Second, a multi-objective optimization problem using the epsilon-constraint method is solved to obtain Pareto optimal solutions. Third, an extension to multi-loop systems is demonstrated. In summary, the design automation framework integrates several elements together as a step toward a more comprehensive solution of 3D packing and routing problems with both geometric and physics considerations.

Automated Layout Generation Methods for 2D Spatial Packing

Development of a computationally-tractable design method for combined multi-physics optimization of packing and routing problems, at a relevant scale, within compact packaging volumes, will offer benefits across several engineering domains. But for performing multi-physics packing and routing optimization, the generation of spatially feasible initial layouts is essential. Three new and computationally efficient methods are demonstrated in this article to produce automatically interference-free 2D geometric layouts. First, a novel 2D force-directed layout method (FDLM) is proposed that implicitly ensures noninterference between components and/or the interconnect network by utilizing spring force theory without using explicit geometric constraints. Second, the A* algorithm, a well-established 2D shortest path algorithm (SPA), has been modified significantly to perform efficient routing of complex interconnect systems. Third, a new geometric topology (GT) enumeration algorithm is presented that produces all unique interconnect routing configurations for given multi-component system architecture. These layout generation methods are then compared with respect to average computational efficiencies and average success rates in attaining feasible layouts for a restricted class of topologies, including evaluation of how the methods scale to problems with an increased number of components. Limitations and future work items for each method are discussed. These methods are presented as an important step toward solution strategies that are compatible with the currently unmet challenges of real-world 2D and 3D combined packing and routing problems, including efficient navigation of the space of discrete options for interconnect geometric topology, as well as scaling to more complex problems.

Towards 200mm 3D RF interposer technology

With the advent of modern and autonomous electronics, applications using RF (radio frequencies) up to millimeter waves and beyond are proliferating. The systems integration becomes increasingly challenging due to variety of devices and passives that typically compose such RF modules, and careful choices of materials are needed for low loss interconnects. One way to minimize RF losses is to integrate the module with high performance interconnect using Si technology, where the different device are mounted on the interposer and the passive are integrated into the silicon. Thanks to the TSV (Through Silicon Via) technology and use of High Resistivity Si substrate, it is possible to have small form factor modules. Such integration approach allows to benefit from the well-established base of 200mm foundries together with the recent progress made in High Resistivity substrate manufacturing. In this work, the process development of a 3D RF interposer technology based on a 200mm process line is reported. The build-up contains 2 levels of metals processed by Cu damascene technology, including a thick 2μm top metal for the lower frequencies applications, an integrated MIM (Metal Insulator Metal) capacitor and use trough silicon via in 5kOhm high resistivity 85μm thick substrate. The TSV are 20μm diameter and 85μm deep made in via first manner with via reveal using temporary carrier handling. Various RF passivation techniques for the silicon have been investigated and a comparison to quartz based on similar test structure is discussed.. Variety of passive devices, transmission line and filter have been processed and characterized. The technology yields 1μm pitch interconnect routing layer, a line loss of 0.34 dB/mm at 40 GHz, and high quality factors inductors larger than 30.