logic emulation Latest Research Papers

High quality hypergraph partitioning for logic emulation

Integration ◽

10.1016/j.vlsi.2021.11.005 ◽

2021 ◽

Author(s):

Benzheng Li ◽

Zhongdong Qi ◽

Zhengguang Tang ◽

Xiyi He ◽

Hailong You

Keyword(s):

High Quality ◽

Hypergraph Partitioning ◽

Logic Emulation

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Improving FPGA-Based Logic Emulation Systems through Machine Learning

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3399595 ◽

2020 ◽

Vol 25 (5) ◽

pp. 1-20

Author(s):

Anthony Agnesina ◽

Sung Kyu Lim ◽

Etienne Lepercq ◽

Jose Escobedo Del Cid

Keyword(s):

Machine Learning ◽

Logic Emulation

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Challenges in Large FPGA-based Logic Emulation Systems

Proceedings of the 2018 International Symposium on Physical Design - ISPD '18 ◽

10.1145/3177540.3177542 ◽

2018 ◽

Cited By ~ 4

Author(s):

William N.N. Hung ◽

Richard Sun

Keyword(s):

Logic Emulation

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Logic emulation in the megaLUT era — Moore's Law beats Rent's Rule

2014 International Conference on Field-Programmable Technology (FPT) ◽

10.1109/fpt.2014.7082742 ◽

2014 ◽

Cited By ~ 2

Author(s):

Mike Butts

Keyword(s):

Moore’S Law ◽

Moore's Law ◽

Logic Emulation

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Logic emulation with forced assertions: A methodology for rapid functional verification and debug

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643605 ◽

2013 ◽

Cited By ~ 1

Author(s):

Somnath Banerjee ◽

Tushar Gupta ◽

Sanjay Gupta

Keyword(s):

Functional Verification ◽

Logic Emulation

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Enhanced tracing and visibility in logic emulation environment by optimized design slicing

2012 4th Asia Symposium on Quality Electronic Design (ASQED) ◽

10.1109/acqed.2012.6320500 ◽

2012 ◽

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Optimized Design ◽

Logic Emulation

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Efficient Online RTL Debugging Methodology for Logic Emulation Systems

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.87 ◽

2012 ◽

Cited By ~ 5

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Logic Emulation

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Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

2011 3rd Asia Symposium on Quality Electronic Design (ASQED) ◽

10.1109/asqed.2011.6111765 ◽

2011 ◽

Cited By ~ 2

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Parallel Processing ◽

Design Element ◽

Multi Stage ◽

Logic Emulation

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A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

2010 IEEE International Test Conference ◽

10.1109/test.2010.5699267 ◽

2010 ◽

Cited By ~ 1

Author(s):

Shuou Nomura ◽

Karthikeyan Sankaralingam ◽

Ranganathan Sankaralingam1

Keyword(s):

Path Delay ◽

Timing Speculation ◽

Logic Emulation

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Automatic error recovery in targetless logic emulation

10.1109/asqed.2009.5206235 ◽

2009 ◽

Cited By ~ 3

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Error Recovery ◽

Logic Emulation ◽

Automatic Error

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logic emulation
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

High quality hypergraph partitioning for logic emulation

Improving FPGA-Based Logic Emulation Systems through Machine Learning

Challenges in Large FPGA-based Logic Emulation Systems

Logic emulation in the megaLUT era — Moore's Law beats Rent's Rule

Logic emulation with forced assertions: A methodology for rapid functional verification and debug

Enhanced tracing and visibility in logic emulation environment by optimized design slicing

Efficient Online RTL Debugging Methodology for Logic Emulation Systems

Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

Automatic error recovery in targetless logic emulation

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logic emulationRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

High quality hypergraph partitioning for logic emulation

Improving FPGA-Based Logic Emulation Systems through Machine Learning

Challenges in Large FPGA-based Logic Emulation Systems

Logic emulation in the megaLUT era — Moore's Law beats Rent's Rule

Logic emulation with forced assertions: A methodology for rapid functional verification and debug

Enhanced tracing and visibility in logic emulation environment by optimized design slicing

Efficient Online RTL Debugging Methodology for Logic Emulation Systems

Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

Automatic error recovery in targetless logic emulation

logic emulation
Recently Published Documents