Efficient Online RTL Debugging Methodology for Logic Emulation Systems

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.87 ◽

2012 ◽

Cited By ~ 5

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Logic Emulation

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Combinational circuit fault diagnosis using logic emulation

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206347 ◽

2003 ◽

Author(s):

Shyue-Kung Lu ◽

Jian-Long Chen ◽

Cheng-Wen Wu ◽

Ken-Feng Chang ◽

Shi-Yu Huang

Keyword(s):

Fault Diagnosis ◽

Combinational Circuit ◽

Circuit Fault Diagnosis ◽

Logic Emulation

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Circuit partitioning for huge logic emulation systems

32nd Design Automation Conference ◽

10.1145/196244.196365 ◽

1994 ◽

Cited By ~ 28

Author(s):

Nan-Chi Chou ◽

Lung-Tien Liu ◽

Chung-Kuan Cheng ◽

Wei-Jin Dai ◽

Rodney Lindelof

Keyword(s):

Circuit Partitioning ◽

Logic Emulation

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An efficient logic emulation system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.238418 ◽

1993 ◽

Vol 1 (2) ◽

pp. 171-174 ◽

Cited By ~ 70

Author(s):

J. Varghese ◽

M. Butts ◽

J. Batcheller

Keyword(s):

Logic Emulation

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A Real-time Rtl Engineering-change Method Supporting On-line Debugging For Logic-emulation Applications

Proceedings of the 34th Design Automation Conference ◽

10.1109/dac.1997.597125 ◽

2005 ◽

Cited By ~ 2

Author(s):

Wen-Jong Fang ◽

A.C.-H. Wu ◽

Ti-Yen Yen

Keyword(s):

Real Time ◽

Engineering Change ◽

On Line ◽

Logic Emulation

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An efficient logic emulation system

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276356 ◽

2003 ◽

Cited By ~ 41

Author(s):

M. Butts ◽

J. Batcheller ◽

J. Varghese

Keyword(s):

Logic Emulation

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Performance-driven board-level routing for FPGA-based logic emulation

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) ◽

10.1109/iccd.1998.727046 ◽

2002 ◽

Author(s):

W.-K. Mak ◽

D.F. Wong

Keyword(s):

Board Level ◽

Logic Emulation

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Sequential circuit fault simulation using logic emulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.712103 ◽

1998 ◽

Vol 17 (8) ◽

pp. 724-736 ◽

Cited By ~ 47

Author(s):

Shih-Arn Hwang ◽

Jin-Hua Hong ◽

Cheng-Wen Wu

Keyword(s):

Fault Simulation ◽

Sequential Circuit ◽

Logic Emulation

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High quality hypergraph partitioning for logic emulation

Integration ◽

10.1016/j.vlsi.2021.11.005 ◽

2021 ◽

Author(s):

Benzheng Li ◽

Zhongdong Qi ◽

Zhengguang Tang ◽

Xiyi He ◽

Hailong You

Keyword(s):

High Quality ◽

Hypergraph Partitioning ◽

Logic Emulation

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Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

2011 3rd Asia Symposium on Quality Electronic Design (ASQED) ◽

10.1109/asqed.2011.6111765 ◽

2011 ◽

Cited By ~ 2

Author(s):

Somnath Banerjee ◽

Tushar Gupta

Keyword(s):

Parallel Processing ◽

Design Element ◽

Multi Stage ◽

Logic Emulation

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Module generation of complex macros for logic-emulation applications

Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97 ◽

10.1145/258305.258314 ◽

1997 ◽

Cited By ~ 1

Author(s):

Wen-Jong Fang ◽

Allen C.-H. Wu ◽

Duan-Ping Chen

Keyword(s):

Logic Emulation

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