scholarly journals A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

2010 ◽  
Author(s):  
Shuou Nomura ◽  
Karthikeyan Sankaralingam ◽  
Ranganathan Sankaralingam1
Keyword(s):  
Path Delay ◽  
Timing Speculation ◽  
Logic Emulation

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

Circuit partitioning for huge logic emulation systems

1994 ◽  
Author(s):  
Nan-Chi Chou ◽  
Lung-Tien Liu ◽  
Chung-Kuan Cheng ◽  
Wei-Jin Dai ◽  
Rodney Lindelof
Keyword(s):  
Circuit Partitioning ◽  
Logic Emulation

A new classification of path-delay fault testability in terms of stuck-at faults

2004 ◽  
Vol 19 (6) ◽  
pp. 955-964 ◽  
Author(s):  
Subhashis Majumder ◽  
Bhargab B. Bhattacharya ◽  
Vishwani D. Agrawal ◽  
Michael L. Bushnell
Keyword(s):  
Path Delay ◽  
New Classification ◽  
Delay Fault ◽  
Path Delay Fault

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

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