Active-Mode Leakage Reduction with Data-Retained Power Gating

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.251 ◽

2013 ◽

Cited By ~ 1

Author(s):

Andrew B. Kahng ◽

Seokhyeong Kang ◽

Bongil Park

Keyword(s):

Power Gating ◽

Active Mode ◽

Leakage Reduction

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Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

IEICE Electronics Express ◽

10.1587/elex.8.1322 ◽

2011 ◽

Vol 8 (16) ◽

pp. 1322-1329

Author(s):

Huan Minh Vo ◽

Chul-Moon Jung ◽

Eun-Sub Lee ◽

Kyeong-Sik Min

Keyword(s):

Power Gating ◽

Active Mode ◽

Carry Select Adder

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Sub-clock power-gating technique for minimising leakage power during active mode

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763026 ◽

2011 ◽

Cited By ~ 8

Author(s):

J N Mistry ◽

B M Al-Hashimi ◽

D Flynn ◽

S Hill

Keyword(s):

Leakage Power ◽

Power Gating ◽

Active Mode

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Active mode leakage reduction using fine-grained forward body biasing strategy

Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04 ◽

10.1145/1013235.1013277 ◽

2004 ◽

Cited By ~ 1

Author(s):

Vishal Khandelwal ◽

Ankur Srivastava

Keyword(s):

Active Mode ◽

Leakage Reduction ◽

Fine Grained ◽

Body Biasing

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A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) ◽

10.1109/vlsid.2007.10 ◽

2007 ◽

Cited By ~ 6

Author(s):

Soumyaroop Roy ◽

Srinivas Katkoori ◽

Nagarajan Ranganathan

Keyword(s):

Reduction Technique ◽

Power Gating ◽

Leakage Reduction ◽

Functional Units

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Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

International Journal on Intelligent Electronic Systems ◽

10.18000/ijies.30133 ◽

2014 ◽

Vol 8 (1) ◽

pp. 8-13

Author(s):

Bhanupriya Bhargava ◽

Pradeep Kumar Sharma ◽

Shyam Akashe

Keyword(s):

Comparative Analysis ◽

Logic Circuit ◽

Power Gating ◽

Voltage Level ◽

Leakage Reduction ◽

Reduction Techniques ◽

Sequential Logic

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A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers ◽

10.1109/isscc.2013.6487753 ◽

2013 ◽

Cited By ~ 13

Author(s):

H. Pilo ◽

C. A. Adams ◽

I. Arsovski ◽

R. M. Houle ◽

S. M. Lamphier ◽

...

Keyword(s):

Power Supply ◽

Low Energy ◽

Power Gating ◽

Leakage Reduction ◽

Soi Technology

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Synthesis and implementation of active mode power gating circuits

Proceedings of the 47th Design Automation Conference on - DAC '10 ◽

10.1145/1837274.1837395 ◽

2010 ◽

Cited By ~ 4

Author(s):

Jun Seomun ◽

Insup Shin ◽

Youngsoo Shin

Keyword(s):

Power Gating ◽

Active Mode

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Innovative power gating for leakage reduction

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4541731 ◽

2008 ◽

Cited By ~ 15

Author(s):

Masud H. Chowdhury ◽

Juliana Gjanci ◽

Pervez Khaled

Keyword(s):

Power Gating ◽

Leakage Reduction

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POWER GATING TECHNIQUES FOR LEAKAGE REDUCTION IN CMOS CIRCUITS - A BRIEF SURVEY

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.4.1.6032 ◽

2016 ◽

Vol 4 (1) ◽

pp. 20

Author(s):

KAVITHA M. ◽

GOVINDARAJ T. ◽

◽

Keyword(s):

Cmos Circuits ◽

Power Gating ◽

Leakage Reduction

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Leakage Reduction of DTGAL Circuits with MTCMOS Power-Gating

2010 International Conference on Electrical and Control Engineering ◽

10.1109/icece.2010.1139 ◽

2010 ◽

Author(s):

Lifang Ye ◽

Jianping Hu ◽

Binbin Liu

Keyword(s):

Power Gating ◽

Leakage Reduction

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