A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) ◽

10.1109/vlsid.2007.10 ◽

2007 ◽

Cited By ~ 6

Author(s):

Soumyaroop Roy ◽

Srinivas Katkoori ◽

Nagarajan Ranganathan

Keyword(s):

Reduction Technique ◽

Power Gating ◽

Leakage Reduction ◽

Functional Units

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Novel Standby Leakage Reduction Technique in SRAM Cell with Enhanced Read Data Stability by Dynamically Varying the Cell Ratio and Pull-up Ratio using Wordline

2020 IEEE 17th India Council International Conference (INDICON) ◽

10.1109/indicon49873.2020.9342517 ◽

2020 ◽

Author(s):

Arjun Singh Yadav ◽

Ankur Beohar ◽

Sunanda Ambulker

Keyword(s):

Reduction Technique ◽

Cell Ratio ◽

Leakage Reduction ◽

Sram Cell

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Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits

2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA) ◽

10.1109/icscan.2018.8541204 ◽

2018 ◽

Cited By ~ 2

Author(s):

G Amuthavalli ◽

R Gunasundari

Keyword(s):

Short Pulse ◽

Reduction Technique ◽

Pulse Power ◽

Combinational Circuits ◽

Leakage Reduction ◽

Subthreshold Leakage

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A Framework for Power-Gating Functional Units in Embedded Microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2005774 ◽

2009 ◽

Vol 17 (11) ◽

pp. 1640-1649 ◽

Cited By ~ 30

Author(s):

S. Roy ◽

N. Ranganathan ◽

S. Katkoori

Keyword(s):

Power Gating ◽

Functional Units

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A Novel Leakage Reduction Technique for Ultra-Low Power VLSI Chips

Proceedings of First International Conference on Information and Communication Technology for Intelligent Systems: Volume 1 - Smart Innovation, Systems and Technologies ◽

10.1007/978-3-319-30933-0_18 ◽

2016 ◽

pp. 165-173 ◽

Cited By ~ 1

Author(s):

Vijay Kumar Magraiya ◽

Tarun Kumar Gupta ◽

Krishna Kant

Keyword(s):

Low Power ◽

Reduction Technique ◽

Ultra Low Power ◽

Leakage Reduction ◽

Vlsi Chips

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Trade-off analysis of fine-grained power gating methods for functional units in a CPU

2012 IEEE COOL Chips XV ◽

10.1109/coolchips.2012.6216587 ◽

2012 ◽

Cited By ~ 2

Author(s):

Weihan Wang ◽

Yuya Ohta ◽

Yoshifumi Ishii ◽

Kimiyoshi Usami ◽

Hideharu Amano

Keyword(s):

Power Gating ◽

Trade Off ◽

Fine Grained ◽

Functional Units

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GPGPU Functional Units Power Gating for Leakage Energy Reduction

Journal of Computing Science and Engineering ◽

10.5626/jcse.2020.14.3.102 ◽

2020 ◽

Vol 14 (3) ◽

pp. 102-111

Author(s):

Xin Wang ◽

Wei Zhang

Keyword(s):

Energy Reduction ◽

Power Gating ◽

Functional Units

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Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

International Journal on Intelligent Electronic Systems ◽

10.18000/ijies.30133 ◽

2014 ◽

Vol 8 (1) ◽

pp. 8-13

Author(s):

Bhanupriya Bhargava ◽

Pradeep Kumar Sharma ◽

Shyam Akashe

Keyword(s):

Comparative Analysis ◽

Logic Circuit ◽

Power Gating ◽

Voltage Level ◽

Leakage Reduction ◽

Reduction Techniques ◽

Sequential Logic

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Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

IPSJ Transactions on System LSI Design Methodology ◽

10.2197/ipsjtsldm.4.182 ◽

2011 ◽

Vol 4 ◽

pp. 182-192 ◽

Cited By ~ 2

Author(s):

Zhao Lei ◽

Daisuke Ikebuchi ◽

Kimiyoshi Usami ◽

Mitaro Namiki ◽

Masaaki Kondo ◽

...

Keyword(s):

Power Gating ◽

Fine Grained ◽

Design And Implementation ◽

Functional Units

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A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers ◽

10.1109/isscc.2013.6487753 ◽

2013 ◽

Cited By ~ 13

Author(s):

H. Pilo ◽

C. A. Adams ◽

I. Arsovski ◽

R. M. Houle ◽

S. M. Lamphier ◽

...

Keyword(s):

Power Supply ◽

Low Energy ◽

Power Gating ◽

Leakage Reduction ◽

Soi Technology

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A novel ground bounce reduction technique using four step power gating

2013 Students Conference on Engineering and Systems (SCES) ◽

10.1109/sces.2013.6547487 ◽

2013 ◽

Cited By ~ 2

Author(s):

Y. Kumar ◽

S. Paliwal ◽

C. K. Rai ◽

S. K. Balasubramanian

Keyword(s):

Reduction Technique ◽

Power Gating ◽

Ground Bounce

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