scholarly journals Sub-clock power-gating technique for minimising leakage power during active mode

2011 ◽  
Author(s):  
J N Mistry ◽  
B M Al-Hashimi ◽  
D Flynn ◽  
S Hill
Keyword(s):  
Leakage Power ◽  
Power Gating ◽  
Active Mode

scholarly journals Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

2011 ◽  
Vol 8 (16) ◽  
pp. 1322-1329
Author(s):  
Huan Minh Vo ◽  
Chul-Moon Jung ◽  
Eun-Sub Lee ◽  
Kyeong-Sik Min
Keyword(s):  
Power Gating ◽  
Active Mode ◽  
Carry Select Adder

scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

scholarly journals ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

10.6036/10108 ◽  
2022 ◽  
Vol 97 (1) ◽  
pp. 79-84
Author(s):  
RUBAN GLADWIN ◽  
NEHRU KASTHURI
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Cyber Security ◽  
Energy Recovery ◽  
High Energy ◽  
Leakage Power ◽  
Handheld Devices ◽  
Power Gating ◽  
Hybrid Energy ◽  
Adiabatic Logic

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

2019 ◽  
Vol 7 (3) ◽  
pp. 11-18
Author(s):  
Yogesh Kulshethra ◽  
Manish Kule
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Leakage Power ◽  
Power Gating ◽  
Design Constraint ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Look Ahead ◽  
Simulation Results ◽  
Gating Scheme

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

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