scholarly journals Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

2011 ◽  
Vol 8 (16) ◽  
pp. 1322-1329
Author(s):  
Huan Minh Vo ◽  
Chul-Moon Jung ◽  
Eun-Sub Lee ◽  
Kyeong-Sik Min
Keyword(s):  
Power Gating ◽  
Active Mode ◽  
Carry Select Adder

scholarly journals Active Mode Subclock Power Gating

2014 ◽  
Vol 22 (9) ◽  
pp. 1898-1908 ◽  
Author(s):  
Jatin N. Mistry ◽  
James Myers ◽  
Bashir M. Al-Hashimi ◽  
David Flynn ◽  
John Biggs ◽  
...  
Keyword(s):  
Power Gating ◽  
Active Mode

Synthesis of Active-Mode Power-Gating Circuits

2012 ◽  
Vol 31 (3) ◽  
pp. 391-403 ◽  
Author(s):  
Jun Seomun ◽  
Insup Shin ◽  
Youngsoo Shin
Keyword(s):  
Power Gating ◽  
Active Mode

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

2012 ◽  
Vol E95-C (4) ◽  
pp. 546-554 ◽  
Author(s):  
Benjamin DEVLIN ◽  
Makoto IKEDA ◽  
Kunihiro ASADA
Keyword(s):  
Voltage Scaling ◽  
Power Gating ◽  
Energy Minimum

Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

2019 ◽  
Vol 14 ◽  
Author(s):  
Teresa V.V ◽  
Anand. B
Keyword(s):  
Research Work ◽  
Low Complexity ◽  
Propagation Delay ◽  
Maximum Speed ◽  
Hyper Spectral ◽  
Ripple Carry Adder ◽  
Minimum Power Consumption ◽  
Carry Select Adder ◽  
The Look ◽  
Propagation Result

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

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