Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Acetylene-Terminated Polyimide Composites for Advanced Electronic Packaging Applications

1989 ◽  
Vol 154 ◽  
Author(s):  
A. Mahammad Ibrahim
Keyword(s):  
Electronic Packaging ◽  
High Speed ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Circuit Board ◽  
Electrical Performance ◽  
Surface Mount ◽  
Plated Through Hole ◽  
Polyimide Composites

AbstractSurface mount technology (SMT) is an electronic packaging technology wherein the leads of electronic components are soldered directly to metallized pads on the surface of a printed circuit board (PCB). The SMT with leadless ceramic chip carriers (LCCCs) is used to design, fabricate, and assemble affordable, high-speed, high-density electronic modules with reduced size and weight and improved electrical performance. In surface mount devices, the LCCCs are soldered directly onto the fabric composite PCB substrate. New high-performance composite substrate materials must be developed to take full advantage of SMT. Fabricating a PCB that will perform reliably throughout its intended life is also an increasingly important requirement, especially if the goal is to satisfy the high reliability required in military applications. Consequently, SMT is driving the development of PCB substrate materials with improved thermal and electrical properties. In our continuing effort to meet these military demands, we evaluated high-temperature resistant/high-performance acetylene-terminated polyimide composites for use in SMT PCBs. This paper focusses on the processing and on the thermal, thermomechanical, and dynamic mechanical properties data developed for these acetylene-terminated polyimide composites for their potential evaluation as PCBs. The characterization includes such properties as in-plane coefficient of thermal expansion (CTE), out-of-plane CTE, and glass transition temperature (Tg), which determine the solder joint reliability, plated-through-hole (PTH) reliability, and dimensional stability.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

Z-Axis Interconnection: A Versatile Technology Solution for High Performance Electronics

2013 ◽  
Vol 2013 (1) ◽  
pp. 000574-000581
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Frank D. Egitto
Keyword(s):  
High Performance ◽  
Metal Layer ◽  
Signal Transmission ◽  
Hole Drilling ◽  
Electrically Conductive ◽  
S Parameter ◽  
Electrically Conductive Adhesive ◽  
Single Structure ◽  
Good Signal ◽  
Interconnect Technology

This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (subcomposites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The z-interconnect based structures offer many advantages over more conventional build-up technologies. For example, it enables designs having increased wiring density, leading to greatly reduced layer counts. When an increase in metal layer counts is required, z-interconnect avoids the cumulative yield loss of sequential (build up) processing. The parallel processing of cores and/or subcomposites leads to reduced fabrication cycle time. Avoidance of through hole drilling allows for reduction or elimination of via stubs that cause signal attenuation at high frequencies. In addition, multilayer rigid-flex packages for a variety of applications are being developed. For these applications, z-interconnect allows for placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs). The process allows fabrication of z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. A number of RF structures have been designed and built with z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form z-interconnects shows good signal transmission to 25GHz. Z-interconnect technology provides unique solutions for next generation complex packaging products.

Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology

2012 ◽  
Vol 2012 (1) ◽  
pp. 000949-000954 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Frank D. Egitto ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Printed Wiring Board ◽  
Potential Cost ◽  
Multiple Substrates ◽  
Electrical Interconnection ◽  
Electrically Conductive Adhesive ◽  
Improved Performance ◽  
Novel Strategy ◽  
Wiring Board

Rigid-flex allows designers to replace multiple substrates interconnected with connectors, wires, and ribbon cables with a single package offering improved performance, reliability, and a potential cost-effective solution. However, processing and materials selection is critical in order to achieve high quality multilayer, rigid-flex structures. To date, there is no technology available which can economically produce high density multilayer rigid-flex with rigid or flex originating from any layer in the stack. In the present study, a novel strategy allowing for multi-layer rigid flex structures is reported. Specifically, metal-to-metal z-axis electrical interconnection among the flexible and rigid elements during lamination to form a single package rigid-flex structure is described. Conductive joints are formed during lamination using an electrically conductive adhesive (ECA). As a result, structures can be fabricated with multiple flexible elements at any arbitrary layer. Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Several classes of flexible materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop high-performance rigid-flex packages. Rigid-flex packages with embedded passives and actives are also being investigated.

Versatile Z-Axis Interconnection for High Performance Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001033-001050
Author(s):  
Rabindra Das ◽  
J. M. Lauffer ◽  
F.D. Egitto
Keyword(s):  
High Performance ◽  
Metal Layer ◽  
Signal Transmission ◽  
Consumer Products ◽  
Next Generation ◽  
Large Area ◽  
Electrically Conductive ◽  
Electrically Conductive Adhesive ◽  
Good Signal ◽  
Interconnect Technology

The demand for high-performance, lightweight, portable computing power for next generation packaging is driving the industry toward miniaturization at a rate not seen before. Electronic packaging is evolving to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and greater heat densities, while being pushed into smaller and smaller footprints. New packaging designs are emerging that require joining (stacking) of multiple packages, joining of different size packages, and flexibility and/or rigidity to accommodate requirements related to size, weight, and complexity. This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (sub-composites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer, high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The Z-interconnect based structures offer many advantages over more conventional build-up technologies, for example, an increase in metal layer counts without the cumulative yield loss of sequential (build up) processing, placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs), allowing for increased wiring density, and reduction or elimination of via stubs that cause signal attenuation, In addition, multilayer rigid-flex packages for a variety of applications are being developed. Several classes of flexible materials that can be used to form high-performance flexible packaging are discussed. Materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop multilayer rigid-flex packages. The process allows fabrication of Z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed. A number of RF structures have been designed and built with Z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form Z-interconnect shows good signal transmission to 25GHz. Z-interconnect substrates provide unique solutions for next generation complex packaging. Collectively, the results suggest that Z-interconnect technology may be attractive for a range of applications, not only where miniaturization is required, such as consumer products, but also in high performance large-area microelectronics such as supercomputers, radio frequency structures, etc.

Recent Advances in Thin Film Multilayer Interconnect Technology for IC Packaging

1987 ◽  
Vol 108 ◽  
Author(s):  
Ronald J. Jensen
Keyword(s):  
Thin Film ◽  
Recent Work ◽  
High Performance ◽  
High Density ◽  
High Conductivity ◽  
Packaging Technology ◽  
Ic Packaging ◽  
The Stability ◽  
Work Done ◽  
Interconnect Technology

ABSTRACTA high-performance packaging technology being developed at Honeywell and a number of other companies uses thin-film processes to pattern high-density interconnections in multiple layers of a high-conductivity conductor (e.g., copper) and a polymer dielectric, primarily polyimide. This paper describes the physical characteristics and unique advantages of this thin film multilayer (TFML) interconnect technology; it then summarizes the results of recent work done at Honeywell in processing TFML structures, assessing the stability and reliability of the materials system, and fabricating test vehicles and demonstration packages.

3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (1) ◽  
pp. 000531-000537 ◽  
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.

Thermal and Mechanical Analysis of a Multichip Module

1992 ◽  
Vol 264 ◽  
Author(s):  
M. S. Hu
Keyword(s):  
High Speed ◽  
Mechanical Analysis ◽  
High Density ◽  
Electrical Performance ◽  
Multichip Module ◽  
Multichip Modules ◽  
Printed Wiring Board ◽  
Proper Design ◽  
Wiring Board ◽  
High Density Packaging

AbstractHigh speed, high density packaging requirements have made multichip modules (MCM) one of the most active areas of research in the electronic industry.High density printed wiring board (PWB) have low production cost and good electrical performance. However, the most questioned issue in application is the reliability. As a result, a thermal and mechanical analysis on a MCM has been conducted to understand its feasibility. The results indicate that with proper design, the components can operate under satisfactory conditions on PWB laminates.

Effective performance improvement of organic thin film transistors with multi-layer modifications

2020 ◽  
Vol 91 (3) ◽  
pp. 30201
Author(s):  
Hang Yu ◽  
Jianlin Zhou ◽  
Yuanyuan Hao ◽  
Yao Ni
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Performance Enhancement ◽  
Organic Thin Film Transistors ◽  
Electrical Performance ◽  
Hole Injection ◽  
Organic Thin Film ◽  
Effective Performance ◽  
Significant Performance ◽  
P Type

Organic thin film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8BTBT) and copper (Cu) electrodes were fabricated. For improving the electrical performance of the original devices, the different modifications were attempted to insert in three different positions including semiconductor/electrode interface, semiconductor bulk inside and semiconductor/insulator interface. In detail, 4,4′,4′′-tris[3-methylpheny(phenyl)amino] triphenylamine (m-MTDATA) was applied between C8BTBTand Cu electrodes as hole injection layer (HIL). Moreover, the fluorinated copper phthalo-cyanine (F16CuPc) was inserted in C8BTBT/SiO2 interface to form F16CuPc/C8BTBT heterojunction or C8BTBT bulk to form C8BTBT/F16CuPc/C8BTBT sandwich configuration. Our experiment shows that, the sandwich structured OTFTs have a significant performance enhancement when appropriate thickness modification is chosen, comparing with original C8BTBT devices. Then, even the low work function metal Cu was applied, a normal p-type operate-mode C8BTBT-OTFT with mobility as high as 2.56 cm2/Vs has been fabricated.

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