Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology

2012 ◽  
Vol 2012 (1) ◽  
pp. 000949-000954 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Frank D. Egitto ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Printed Wiring Board ◽  
Potential Cost ◽  
Multiple Substrates ◽  
Electrical Interconnection ◽  
Electrically Conductive Adhesive ◽  
Improved Performance ◽  
Novel Strategy ◽  
Wiring Board

Rigid-flex allows designers to replace multiple substrates interconnected with connectors, wires, and ribbon cables with a single package offering improved performance, reliability, and a potential cost-effective solution. However, processing and materials selection is critical in order to achieve high quality multilayer, rigid-flex structures. To date, there is no technology available which can economically produce high density multilayer rigid-flex with rigid or flex originating from any layer in the stack. In the present study, a novel strategy allowing for multi-layer rigid flex structures is reported. Specifically, metal-to-metal z-axis electrical interconnection among the flexible and rigid elements during lamination to form a single package rigid-flex structure is described. Conductive joints are formed during lamination using an electrically conductive adhesive (ECA). As a result, structures can be fabricated with multiple flexible elements at any arbitrary layer. Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Several classes of flexible materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop high-performance rigid-flex packages. Rigid-flex packages with embedded passives and actives are also being investigated.

Optoelectronic Packaging for Computer and Communication Systems

1993 ◽  
Vol 323 ◽  
Author(s):  
H. F. Lockwood ◽  
C. A. Armiento
Keyword(s):  
Communication Systems ◽  
High Performance ◽  
Cost Effective ◽  
Hybrid Integration ◽  
Printed Wiring Board ◽  
Single Chip ◽  
Chip Size ◽  
Wiring Board ◽  
On Chip ◽  
The Cost

AbstractThe principal driver behind advanced hardware development in the communications and computer industries can be reduced to an optimal set of parameters related to performance, cost and reliability. High performance systems typically have high functional density. For example, the continuing trend of VLSI is toward reduced feature size, increased wiring density and larger chip size to achieve increasingly higher levels of on-chip functionality. At some point in the cost structure, however, the single chip solution is no longer viable, and monolithic integration gives way to hybrid integration. In this respect, the multichip module fills a void in the packaging/ integration hierarchy between the ever-larger single chip and the printed wiring board.An analogous situation is emerging in optoelectronics. The single chip package with its relatively low system functionality and high cost is giving way to the multi-technology module that integrates optical and electronic functions within a single package. One of the most interesting approaches to the multi-technology module uses a silicon substrate as the platform for hybrid integration of electronics and optoelectronics. It will be argued that this “silicon waferboard” approach is the cost-effective route to manufacturability of high-performance modules for communications and computer systems. Enhanced reliability follows from applying standard IC processing technology at the platform level in the packaging hierarchy.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Optimization of Structural Design for High-Performance Concrete Bridges

1998 ◽  
Vol 1624 (1) ◽  
pp. 132-139
Author(s):  
Mary Lou Ralls ◽  
Ramon L. Carrasquillo ◽  
Ned H. Burns
Keyword(s):  
High Performance ◽  
High Performance Concrete ◽  
High Strength ◽  
Cost Effective ◽  
Concrete Bridges ◽  
Practical Guidelines ◽  
Improved Performance ◽  
Maintenance Requirements ◽  
Design And Construction

High-performance concrete (HPC) bridges can be cost-effective both initially and in the long term, provided the design and construction optimize the improved performance characteristics of HPC. Using the high-strength characteristic of HPC can reduce the required number and size of beams. Using the improved durability characteristics of HPC can reduce maintenance requirements and extend the service life. Practical guidelines help design and construction engineers implement HPC in bridges.

Manufacturing Substrates with Embedded Passives

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002011-002050
Author(s):  
Rabindra N. Das ◽  
Konstantinos I. Papathomas ◽  
John M. Lauffer ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Electrical Characterization ◽  
Printed Wiring Board ◽  
Digital Products ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Wiring Board ◽  
Electronic Assemblies

Passives account for a very large part of today's electronic assemblies. This is particularly true for digital products such as cellular phones, camcorders, computers and several critical defense devices. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on organic multilayered substrates. A variety of thin film capacitor and resistors were utilized to manufacture high-performance embedded passives. The electrical properties of capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide temperature range. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. In both cases, capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Nanocomposite can be directly deposited either by liquid coating or screen printing. Alternatively, nanocomposite thin films can be laminated and capacitor laminate can be used as the base substrate for subsequent build-up processing. For example, Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. The capacitor fabrication is based on a sequential build-up technology employing a first patternable electrode. After patterning of the electrode, RC3 nanocomposite can be laminated within PCB. Embedded passive cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. Reliability of the capacitors was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1000 cycles DTC (Deep Thermal Cycle).

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

A novel strategy for the synthesis of hard carbon spheres encapsulated with graphene networks as a low-cost and large-scalable anode material for fast sodium storage with an ultralong cycle life

2020 ◽  
Vol 7 (2) ◽  
pp. 402-410 ◽  
Author(s):  
Ghulam Yasin ◽  
Muhammad Arif ◽  
Tahira Mehtab ◽  
Muhammad Shakeel ◽  
Muhammad Asim Mushtaq ◽  
...  
Keyword(s):  
Anode Material ◽  
High Performance ◽  
Low Cost ◽  
Cost Effective ◽  
Sodium Ion ◽  
Sodium Ion Batteries ◽  
Carbon Spheres ◽  
Hard Carbon ◽  
Novel Strategy ◽  
Sodium Storage

We designed a cost-effective and novel strategy for the construction of hard carbon spheres enveloped with graphene networks as a high performance anode material for sodium-ion batteries.

Effects of conductor surface condition on signal integrity

Circuit World ◽  
2004 ◽  
Vol 30 (3) ◽  
pp. 11-16 ◽  
Author(s):  
Martin Bayes ◽  
Al Horn
Keyword(s):  
Surface Condition ◽  
Cost Effective ◽  
Dielectric Materials ◽  
Electronic Systems ◽  
Signal Loss ◽  
Printed Wiring Board ◽  
Conductor Surface ◽  
Alternative Test ◽  
Laminate Materials ◽  
Wiring Board

The evolution of digital electronic systems to ever‐faster pulse rise times has placed increased demands on printed wiring board (PWB) materials. Signal loss associated with dielectric materials has driven development and commercialization of cost‐effective low loss laminate materials. In order to provide a better understanding of conductor material and surface finish choices, efforts have been made to quantify the impacts of these factors on loss. An alternative test approach has been identified which provides a measure of conductor performance, decoupled from both system geometry and the influence of laminate material.

3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (1) ◽  
pp. 000531-000537 ◽  
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.

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