Thermomechanical Design for Fine Pitch 3D-IC Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
High Stress ◽  
High Viscosity ◽  
Thermomechanical Properties ◽  
Design Parameters ◽  
Element Analysis ◽  
Package Design ◽  
Fine Pitch ◽  
Silicon Vias

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Silicon Interposer Featuring Novel Electrical and Optical TSVs

2012 ◽  
Author(s):  
Paragkumar A. Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
System Level ◽  
Performance Improvements ◽  
Fine Pitch ◽  
3D Integrated Circuits ◽  
Photonic Interconnects ◽  
Silicon Vias

Three-dimensional (3D) integrated circuits (ICs) yield system level performance improvements by providing high-bandwidth communication as well as opportunity for heterogeneous integration. It is envisioned that an area array of 3D stacked ICs can be interconnected using dense fine-pitch electrical and photonic interconnects on a silicon interposer. This paper presents a mechanically robust “thick” silicon interposer with novel electrical through-silicon vias (TSVs) and optical TSVs. The novel electrical TSVs described include polymer-clad TSVs and polymer-embedded vias. An advantage of using thick silicon interposer is that microchannels can be integrated in the thick silicon interposer to transfer a coolant to the 3D ICs with interlayer microfluidic heat sink or for the direct integration of a microfluidic heat-sink in the silicon interposer. However, as the thickness of silicon interposer increases, TSV electrical parasitics increase. Moreover, the coefficient of thermal expansion (CTE) mismatch between the copper TSV and silicon causes reliability issues. To reduce TSV capacitance as well as to reduce TSV stresses, polymer-clad electrical TSVs were fabricated. Using the same photodefinable polymer used for the cladding of electrical TSVs, optical TSVs were fabricated and characterized.

Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array

2004 ◽  
Vol 126 (4) ◽  
pp. 560-564 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Jenq-Dah Wu
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Thermomechanical Properties ◽  
Creep Model ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Dimensional Finite Element ◽  
Real Behavior ◽  
Thermal Cycling Fatigue

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.

Compliant Stress-Engineered Interconnects for Next-Generation Packaging

2004 ◽  
Author(s):  
Kevin M. Klein ◽  
Suresh K. Sitaraman
Keyword(s):  
Life Stress ◽  
Low Cost ◽  
Intrinsic Stress ◽  
Wafer Level ◽  
Element Analysis ◽  
Operational Conditions ◽  
Technology Roadmap ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Future Demands

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.

Characterization of Thermal Stress Phenomena Induced Into a Packaged Planar Lightwave Circuit Using Fiber Bragg Grating Sensors

2005 ◽  
Author(s):  
Amelia G. Grobnic ◽  
Robert James ◽  
Ping Lu ◽  
Stephen J. Mihailov
Keyword(s):  
Thermal Stress ◽  
Fiber Bragg Grating ◽  
Thermal Sensitivity ◽  
Photonic Devices ◽  
Design Parameters ◽  
Bragg Grating ◽  
Element Analysis ◽  
Package Design ◽  
Planar Lightwave Circuit ◽  
Planar Lightwave

We present a technique for the characterization and analysis of the thermal stress in the optical substrate of packaged photonic devices. This method allows optimization of the package geometry in order to improve the passive compensation of the thermal sensitivity of photonic devices. To the best of our knowledge, we report for the first time the use of strongly chirped, weakly apodized fiber Bragg grating (FBG) sensors to evaluate the stress distribution induced by the package in the planar lightwave circuit (PLC) substrate. We also evaluated the substrate thermal stress using finite element analysis (FEA). We investigated some of the package design parameters that can be used to control and tune the amount of stress that can be applied to the photonic device optical substrate. Our goal is to optimize the design of a package that applies tensile stress to the optical device to compensate unwanted effects due to ambient temperature variation.

Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000635-000673
Author(s):  
Paragkumar Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Stress Reduction ◽  
Insertion Loss ◽  
Coefficient Of Thermal Expansion ◽  
Stress Generation ◽  
High Yield ◽  
High Resistivity ◽  
Silicon Substrates ◽  
The Novel ◽  
Fine Pitch ◽  
Silicon Vias

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias. The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield. In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.

Stress Distribution Effect on a Stacked-Die QFN Package Manufacturing Processes

2011 ◽  
Vol 462-463 ◽  
pp. 1273-1278
Author(s):  
I. Abdullah ◽  
Azman Jalar ◽  
Shahrum Abdullah ◽  
M.F. Rosle ◽  
Mohd Faridz Mod Yunoh
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Stress ◽  
Three Dimensional ◽  
Manufacturing Processes ◽  
Stress Effect ◽  
Package Design ◽  
Induced Stress ◽  
Die Attach ◽  
Low Modulus ◽  
Element Technique

In the last decade, failure of microelectronic devices has become a prominent field of research all across the world. The results of this of failure analysis allow an engineer to choose package geometries and materials which reduce the risk of failure. This paper is meant to relate the stress effect on material properties during Quad Flat No-Leads (QFN) stacked-die packages manufacturing processes. To achieve the study, the finite element technique was used to perform an extensive structural analysis on a QFN package design once it was verified by related experiments. A QFN unit was developed in three dimensional geometry with various materials be will simulated in order to determine the location of failure. The induced stress results were also measured in the maximum value, indicating the low modulus and coefficient of thermal expansion (CTE) in the packaging material were important for reducing high stress during the manufacturing stages. However, numerical simulation demonstrated that the stress developments increased exponentially when the die attach temperature increased. Therefore, the induced stress can be relieved by having high die attach process temperature with an adequate bonding force and time. It was vital to control the induced stress in package materials during die attachment process for ensuring the reliability level of QFN packages.

The Finite Element Analysis of the Rollers in a Rotary Steerable Drilling Tool

2013 ◽  
Vol 390 ◽  
pp. 641-645
Author(s):  
Guang Wei Zhang ◽  
Li You ◽  
Zhao Li
Keyword(s):  
Low Cost ◽  
Major Change ◽  
Drill String ◽  
Design Parameters ◽  
Directional Drilling ◽  
Element Analysis ◽  
Rotary Drilling ◽  
Drilling Tool ◽  
Thrust Bearings ◽  
Drilling Technology

Rotary steerable system (RSS) is a system complete the oriented features in real-time while a drill string rotary drilling. It is a major change since the 1990s in directional drilling technology. RSSs drilling frictional and torsional resistance is small, has a high drilling speed, low cost, the well trajectory is smooth and easy to control, it is considered to be the development direction of modern steering drilling technology .When the system working ,drilling pressure and torque are passed by the thrust bearings in the controlled bend sub oriented tool; therefore it is necessary to analysis the rollers load distribution to verify the design parameters of variation cardan shaft, thrust bearings and roller are correct or not, This article analyzed thrust bearings rollers by ANSYS. Determine its maximum stress, etc. Providing more intuitive and scientific basis for its structural optimization [1].

Finite Element Analysis of Functionally Graded Thick-Cylinders Subjected to Mechanical and Thermal Loads

2012 ◽  
Author(s):  
Jasem A. Ahmed ◽  
M. A. Wahab
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Material Properties ◽  
Radial Direction ◽  
Coefficient Of Thermal Expansion ◽  
Stress Component ◽  
Pressure Vessels ◽  
Functionally Graded ◽  
Design Parameters ◽  
Element Analysis

Functionally graded materials (FGM) are used to design structures used in high temperature environment. Hybrid pressure vessels can be designed from FGMs to incorporate improved strength, weight reduction, thermal properties, impact resistance etc. Progressive research in this area will lead to the determination of optimum design parameters and provide insight in developing manufacturing techniques of full-scale hybrid pressure vessels and experimental validation. In future, an accurate damage model will help in planning component examinations in a selective manner in order to provide useful information about material condition and predict the remaining life of the structure. A functionally graded thick-walled cylindrical vessel with varying material properties in the radial direction is considered. The cylinder is assumed to be made of one phase spatially dispersed in a matrix of another. Volume fractions of the phases are assumed to vary along the radial direction according to power laws. The gradation is represented by dividing the radial domain into finite sub-domains. The effective material properties such as modulus of elasticity, Poisson’s ratio, thermal conductivity and coefficient of thermal expansion are estimated using Mori-Tanaka [1], Hashin–Shtrikman [2], Hatta-Taya [3] and Rosen-Hashin [4] relations. The hollow cylinder is subjected to axisymmetric mechanical and thermal loadings. Finite Element Analysis is performed using a commercial package, ANSYS, to obtain temperature and stress component distribution along the thickness of the cylinder. Results are presented graphically to show the effect of internal pressure, temperature change, and gradient variation of material properties on stress components throughout the thickness.

scholarly journals Thermomechanical Analysis of Ceramic Composites Using Object Oriented Finite Element Analysis

2021 ◽  
Author(s):  
Satyanarayan Patel
Keyword(s):  
Finite Element ◽  
Thermal Expansion ◽  
Coefficient Of Thermal Expansion ◽  
Object Oriented ◽  
Thermomechanical Analysis ◽  
Ceramic Composites ◽  
Thermomechanical Properties ◽  
Element Analysis ◽  
Simulation Techniques ◽  
Barrier Coating

This chapter discussed the object oriented finite element (OOF2)-based studies for ceramic composites. OOF2 is an effective method that uses an actual microstructure image of the material/composites for simulation. The effect of filler inclusions on the thermomechanical properties (coefficient of thermal expansion, thermal conductivity, Young’s modulus, stress and strain) is discussed. For this purpose, various ceramics composites (thermal barrier coating and ferroelectric based) are considered at homogeneous and heterogeneous temperature/stress conditions. The maximum stress is found at the interface of the filler/matrix due to their mismatch of thermal expansion coefficient. Further, residual and localized interface stress distributions are evaluated to analyze the composite’s failure behavior. The possible integration of OOF2 with other simulation techniques is also explored.

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