Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000635-000673
Author(s):  
Paragkumar Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Stress Reduction ◽  
Insertion Loss ◽  
Coefficient Of Thermal Expansion ◽  
Stress Generation ◽  
High Yield ◽  
High Resistivity ◽  
Silicon Substrates ◽  
The Novel ◽  
Fine Pitch ◽  
Silicon Vias

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias. The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield. In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.

Thermomechanical Design for Fine Pitch 3D-IC Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
High Stress ◽  
High Viscosity ◽  
Thermomechanical Properties ◽  
Design Parameters ◽  
Element Analysis ◽  
Package Design ◽  
Fine Pitch ◽  
Silicon Vias

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

Silicon Interposer Featuring Novel Electrical and Optical TSVs

2012 ◽  
Author(s):  
Paragkumar A. Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
System Level ◽  
Performance Improvements ◽  
Fine Pitch ◽  
3D Integrated Circuits ◽  
Photonic Interconnects ◽  
Silicon Vias

Three-dimensional (3D) integrated circuits (ICs) yield system level performance improvements by providing high-bandwidth communication as well as opportunity for heterogeneous integration. It is envisioned that an area array of 3D stacked ICs can be interconnected using dense fine-pitch electrical and photonic interconnects on a silicon interposer. This paper presents a mechanically robust “thick” silicon interposer with novel electrical through-silicon vias (TSVs) and optical TSVs. The novel electrical TSVs described include polymer-clad TSVs and polymer-embedded vias. An advantage of using thick silicon interposer is that microchannels can be integrated in the thick silicon interposer to transfer a coolant to the 3D ICs with interlayer microfluidic heat sink or for the direct integration of a microfluidic heat-sink in the silicon interposer. However, as the thickness of silicon interposer increases, TSV electrical parasitics increase. Moreover, the coefficient of thermal expansion (CTE) mismatch between the copper TSV and silicon causes reliability issues. To reduce TSV capacitance as well as to reduce TSV stresses, polymer-clad electrical TSVs were fabricated. Using the same photodefinable polymer used for the cladding of electrical TSVs, optical TSVs were fabricated and characterized.

Advanced Silicon Interposer for High density and High Integration Electronic Packages

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000865-000905
Author(s):  
SATORU KUMOCHI ◽  
Sumio Koiwa ◽  
Kosuke Suzuki ◽  
Yoshitaka Fukuoka
Keyword(s):  
System Integration ◽  
High Density ◽  
High Resistivity ◽  
Through Silicon Vias ◽  
Passive Device ◽  
Fine Pitch ◽  
Mems Technology ◽  
Cte Mismatch ◽  
Silicon Vias ◽  
Electrical Loss

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

Comparison of Fabrication Process Capability and Electrical Performance with Silicon and Glass Interposers

2014 ◽  
Vol 2014 (1) ◽  
pp. 000376-000381 ◽  
Author(s):  
Satoru Kuramochi ◽  
Sumio Koiwa ◽  
Takamasa Takano ◽  
Miyuki Akazawa ◽  
Hiroshi Mawatari ◽  
...  
Keyword(s):  
System Integration ◽  
Electrical Performance ◽  
High Resistivity ◽  
Electronic Systems ◽  
The Past ◽  
Fine Pitch ◽  
Large Panel ◽  
Silicon Vias ◽  
Electrical Loss ◽  
Thick Glass

As electronic product becomes smaller and lighter with an increasing number of function ↚ the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of TSV interposers and TGV interposers with fine pitch high aspect ratio through vias.

Parallel-Path Compliant Structures as Electrical Interconnects

2010 ◽  
Author(s):  
Raphael Okereke ◽  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
Dielectric Materials ◽  
High Yield ◽  
Mechanical Reliability ◽  
Parallel Path ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Compliant Interconnect ◽  
Low K

The coefficient of thermal expansion (CTE) mismatch between a die and an organic substrate generates high stresses in the die when underfilled solder bumps are used. These high stresses could crack or delaminate low-K dielectric materials in the next-generation flip-chip devices. In addition to such on-chip failures, the solder interconnects could fail due to thermo-mechanical fatigue, especially when the interconnect dimensions are scaled down to meet fine-pitch requirements. To address these reliability issues, compliant interconnects have been proposed to alleviate the thermo-mechanical stresses in the chip assembly. Some of the challenges to be addressed with compliant interconnects are: higher electrical parasitic compared to solder bumps, cost-effective fabrication, and high-yield, fine-pitch assembly process. This paper presents a study on a parallel-path compliant interconnect design which attempts to balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Also, these interconnects can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermo-mechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermo-mechanical reliability of a parallel-path compliant interconnect.

Nanoscale Self-Assembly Using Ion and Electron Beam Techniques: A Rapid Review

MRS Advances ◽  
2020 ◽  
Vol 5 (64) ◽  
pp. 3507-3520
Author(s):  
Chunhui Dai ◽  
Kriti Agarwal ◽  
Jeong-Hyun Cho
Keyword(s):  
Electron Beam ◽  
Self Assembly ◽  
Ion Beam ◽  
Three Dimensional ◽  
The Self ◽  
Stress Generation ◽  
Rapid Review ◽  
High Yield ◽  
3D Nanostructures ◽  
Self Assembled

AbstractNanoscale self-assembly, as a technique to transform two-dimensional (2D) planar patterns into three-dimensional (3D) nanoscale architectures, has achieved tremendous success in the past decade. However, an assembly process at nanoscale is easily affected by small unavoidable variations in sample conditions and reaction environment, resulting in a low yield. Recently, in-situ monitored self-assembly based on ion and electron irradiation has stood out as a promising candidate to overcome this limitation. The usage of ion and electron beam allows stress generation and real-time observation simultaneously, which significantly enhances the controllability of self-assembly. This enables the realization of various complex 3D nanostructures with a high yield. The additional dimension of the self-assembled 3D nanostructures opens the possibility to explore novel properties that cannot be demonstrated in 2D planar patterns. Here, we present a rapid review on the recent achievements and challenges in nanoscale self-assembly using electron and ion beam techniques, followed by a discussion of the novel optical properties achieved in the self-assembled 3D nanostructures.

Ten-Vertex Polyhedral Monocarbaborane Chemistry. The Novel High-Yield Formation of the Ten-Vertex closo Compound [6-(PMe2Ph)-closo-1-CB9H9] from the Thermolysis of [8,8-(PMe2Ph)2-nido-8,7-PtCB9H11]

1993 ◽  
Vol 58 (12) ◽  
pp. 2924-2935 ◽  
Author(s):  
Jane H. Jones ◽  
Bohumil Štíbr ◽  
John D. Kennedy ◽  
Mark Thornton-Pett
Keyword(s):  
Nmr Spectroscopy ◽  
Diffraction Analysis ◽  
High Yield ◽  
Monoclinic Space Group ◽  
The Novel ◽  
X Ray Diffraction ◽  
Metal Centre ◽  
X Ray ◽  
Yield Formation ◽  
Boiling Toluene

Thermolysis of [8,8-(PMe2Ph)2-nido-8,7-PtCB9H11] in boiling toluene solution results in an elimination of the platinum centre and cluster closure to give the ten-vertex closo species [6-(PMe2Ph)-closo-1-CB9H9] in 85% yield as a colourles air stable solid. The product is characterized by NMR spectroscopy and single-crystal X-ray diffraction analysis. Crystals (from hexane-dichloromethane) are monoclinic, space group P21/c, with a = 903.20(9), b = 1 481.86(11), c = 2 320.0(2) pm, β = 97.860(7)° and Z = 8, and the structure has been refined to R(Rw) = 0.045(0.051) for 3 281 observed reflections with Fo > 2.0σ(Fo). The clean high-yield elimination of a metal centre from a polyhedral metallaborane or metallaheteroborane species is very rare.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Heterostructures of GaAs and AlAs on Silicon: X-Ray Analysis and Excimer Laser Annealing

1988 ◽  
Vol 116 ◽  
Author(s):  
A. Georgakilas ◽  
M. Fatemi ◽  
L. Fotiadis ◽  
A. Christou
Keyword(s):  
Molecular Beam Epitaxy ◽  
Dislocation Density ◽  
Excimer Laser ◽  
Molecular Beam ◽  
Laser Annealing ◽  
High Resistivity ◽  
Silicon Substrates ◽  
Excimer Laser Annealing ◽  
X Ray ◽  
High Resistivity Silicon

AbstractOne micron thick AlAs/GaAs structures have been deposited by molecular beam epitaxy onto high resistivity silicon substrates. Subsequent to deposition, it is shown that Excimer laser annealing up to 120mJ/cm2 at 248nm improves the GaAs mobility to approximately 2000cm2 /v-s. Dislocation density, however, did not decrease up to 180mJ/cm2 showing that improvement in transport properties may not be accompanied by an associated decrease in dislocation density at the GaAs/Si interface.

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