Optoelectronic Packaging for Computer and Communication Systems

1993 ◽  
Vol 323 ◽  
Author(s):  
H. F. Lockwood ◽  
C. A. Armiento
Keyword(s):  
Communication Systems ◽  
High Performance ◽  
Cost Effective ◽  
Hybrid Integration ◽  
Printed Wiring Board ◽  
Single Chip ◽  
Chip Size ◽  
Wiring Board ◽  
On Chip ◽  
The Cost

AbstractThe principal driver behind advanced hardware development in the communications and computer industries can be reduced to an optimal set of parameters related to performance, cost and reliability. High performance systems typically have high functional density. For example, the continuing trend of VLSI is toward reduced feature size, increased wiring density and larger chip size to achieve increasingly higher levels of on-chip functionality. At some point in the cost structure, however, the single chip solution is no longer viable, and monolithic integration gives way to hybrid integration. In this respect, the multichip module fills a void in the packaging/ integration hierarchy between the ever-larger single chip and the printed wiring board.An analogous situation is emerging in optoelectronics. The single chip package with its relatively low system functionality and high cost is giving way to the multi-technology module that integrates optical and electronic functions within a single package. One of the most interesting approaches to the multi-technology module uses a silicon substrate as the platform for hybrid integration of electronics and optoelectronics. It will be argued that this “silicon waferboard” approach is the cost-effective route to manufacturability of high-performance modules for communications and computer systems. Enhanced reliability follows from applying standard IC processing technology at the platform level in the packaging hierarchy.

Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology

2012 ◽  
Vol 2012 (1) ◽  
pp. 000949-000954 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Frank D. Egitto ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Printed Wiring Board ◽  
Potential Cost ◽  
Multiple Substrates ◽  
Electrical Interconnection ◽  
Electrically Conductive Adhesive ◽  
Improved Performance ◽  
Novel Strategy ◽  
Wiring Board

Rigid-flex allows designers to replace multiple substrates interconnected with connectors, wires, and ribbon cables with a single package offering improved performance, reliability, and a potential cost-effective solution. However, processing and materials selection is critical in order to achieve high quality multilayer, rigid-flex structures. To date, there is no technology available which can economically produce high density multilayer rigid-flex with rigid or flex originating from any layer in the stack. In the present study, a novel strategy allowing for multi-layer rigid flex structures is reported. Specifically, metal-to-metal z-axis electrical interconnection among the flexible and rigid elements during lamination to form a single package rigid-flex structure is described. Conductive joints are formed during lamination using an electrically conductive adhesive (ECA). As a result, structures can be fabricated with multiple flexible elements at any arbitrary layer. Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Several classes of flexible materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop high-performance rigid-flex packages. Rigid-flex packages with embedded passives and actives are also being investigated.

scholarly journals A Review on Terahertz Technologies Accelerated by Silicon Photonics

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1646
Author(s):  
Jingya Xie ◽  
Wangcheng Ye ◽  
Linjie Zhou ◽  
Xuguang Guo ◽  
Xiaofei Zang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Silicon Photonics ◽  
Large Scale ◽  
Cost Effective ◽  
Single Chip ◽  
Photonic Integrated Circuit ◽  
Hybrid Silicon ◽  
The Cost ◽  
Silicon Based ◽  
Thz Applications

In the last couple of decades, terahertz (THz) technologies, which lie in the frequency gap between the infrared and microwaves, have been greatly enhanced and investigated due to possible opportunities in a plethora of THz applications, such as imaging, security, and wireless communications. Photonics has led the way to the generation, modulation, and detection of THz waves such as the photomixing technique. In tandem with these investigations, researchers have been exploring ways to use silicon photonics technologies for THz applications to leverage the cost-effective large-scale fabrication and integration opportunities that it would enable. Although silicon photonics has enabled the implementation of a large number of optical components for practical use, for THz integrated systems, we still face several challenges associated with high-quality hybrid silicon lasers, conversion efficiency, device integration, and fabrication. This paper provides an overview of recent progress in THz technologies based on silicon photonics or hybrid silicon photonics, including THz generation, detection, phase modulation, intensity modulation, and passive components. As silicon-based electronic and photonic circuits are further approaching THz frequencies, one single chip with electronics, photonics, and THz functions seems inevitable, resulting in the ultimate dream of a THz electronic–photonic integrated circuit.

Making E-Training Cost Effective through Quality Assurance

2009 ◽  
pp. 623-631
Author(s):  
Lichia Yiu ◽  
Raymond Saner
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Web Based ◽  
Corporate Learning ◽  
Use Of Technology ◽  
Training Cost ◽  
E Learning ◽  
American Society ◽  
High Level ◽  
The Cost

Since the 1990s, more and more corporate learning has been moved online to allow for flexibility, just-in-time learning, and cost saving in delivering training. This trend has been evolved along with the introduction of Web-based applications for HRM purposes, known as electronic Human Resource Management (e-HRM). By 2005, 39.67% of the corporate learning, among the ASTD (American Society for Training and Development) benchmarking forum companies, was delivered online in comparison to 10.5% in 2001. E-learning has now reached “a high level of (technical) sophistication, both in terms of instructional development and the effective management of resources” in companies with high performance learning function (ASTD, 2006, p.4). The cost per unit, reported by ASTD in its 2006 State of Industry Report, has been declining since 2000 despite the higher training hours received per employee thanks to the use of technology based training delivery and its scalability. However, the overall quality of e-learning either public available in the market or implemented at the workplace remains unstable.

Cost Drivers for 2.5D and 3D Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000334-000346
Author(s):  
Chet Palesko ◽  
E. Jan Vardaman ◽  
Alan Palesko
Keyword(s):  
High Performance ◽  
Specific Activity ◽  
Cost Effective ◽  
Cost Models ◽  
Network Systems ◽  
Cost Drivers ◽  
Technology Applications ◽  
Silicon Vias ◽  
The Cost ◽  
3D Applications

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as a packaging alternative. Miniaturization and high performance product requirements are driving this move – even though in many cases the cost of both 2.5D and 3D is still high. The primary applications for 2.5D interposers with TSVs are GPUs/CPUs, high-end ASICs, and FPGAs. Adoption for FPGAs has already started. The key to the performance gains in recently introduced FPGAs is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer or what Xilinx calls its Stacked Silicon Interconnect technology. Applications for interposers include tablets, gaming, and high-end computing and network systems. The drivers are mainly partitioning large die, integrating single chips into a module, reducing die size where substrate density is the constraint, and using the interposer to minimize the stress on large die that are fabricated with extra-low-k (ELK) dielectrics. The primary applications for 3D solutions are stacked memory cubes and memory plus logic. The true 3D nature of stacking all active silicon allows better miniaturization, but yield issues can quickly drive the cost unacceptably high. This analysis examines the cost drivers for 2.5D and 3D applications. Activity based cost models will be used to analyze the complete cost of fabricating and assembling active die on a silicon interposer and active die stacking on other active die. Total product cost impact - not just the cost of a specific activity - is the focus of this analysis. Since yields play a major role in cost, a sensitivity analysis of the different yields including die yield before wafer probe, die yield after wafer probe, TSV yield, interposer yield, assembly yield, substrate yield, etc. will be presented. The critical yield points in the manufacturing flow and dominant activity cost drivers (equipment, material, and /or labor) will be presented as well as suggested minimum thresholds for 2.5D and 3D technology to be a cost effective technology.

Design and Calibration of MIMU Based on Chip Size Micro Inertial Sensors

2013 ◽  
Vol 849 ◽  
pp. 302-309
Author(s):  
Yun Xu ◽  
Xin Hua Zhu ◽  
Yu Wang
Keyword(s):  
High Performance ◽  
Inertial Sensors ◽  
Low Cost ◽  
Rapid Development ◽  
Experimental Result ◽  
Integrated Navigation ◽  
Bias Stability ◽  
Chip Size ◽  
Order Of Magnitude ◽  
On Chip

With rapid development of micro fabrication technology, the performance of MIMU has gradually improved. The MIMU introduced in this paper is based on the silicon micro machined gyroscope of type MSG7000D and accelerometer of type MSA6000. The volume of it is 3×3×3cm3, the mass is 68.5g and the power consumption is less than 1w. The experimental result shows that the bias stability of the gyroscope and accelerometer for each axis of the designed MIMU is less than 10°/h and 0.5mg respectively. For the non orthogonality in three axes of the structure, MIMU needs to be calibrated. After calibration, the measurement accuracy has improved by an order of magnitude. The designed MIMU can satisfy the requirement of high performance, low cost, light weight and small size for strap-down navigation system, thus it can be widely applied not only to the field of vehicles integrated navigation, attitude measurement but also to the fields of personal goods such as mobile, game consoles and so on.

Approaches to the Design and Processing of Novel Titanium Alloys

2007 ◽  
Vol 29-30 ◽  
pp. 127-130
Author(s):  
Colleen J. Bettles ◽  
Rimma Lapovok ◽  
H.P. Ng ◽  
Dacian Tomus ◽  
Barry C. Muddle
Keyword(s):  
Titanium Alloys ◽  
High Performance ◽  
Powder Processing ◽  
Low Cost ◽  
Cost Effective ◽  
Processing Technologies ◽  
Shape Processing ◽  
New Processing ◽  
The Cost ◽  
Processing Techniques

The range of commercial titanium alloys available is currently extremely restricted, with one alloy (Ti-6Al-4V), and derivatives of it, accounting for a very large proportion of all applications. High performance alloys are costly to fabricate and limited to low-volume applications that can sustain the cost. With the emergence of new processing technologies that promise to reduce significantly the cost of production of titanium metal, especially in powder form, there is an emerging imperative for cost-effective near net shape powder processing techniques to permit the benefit of reduced metal cost to be passed on to higher-volume applications. Equally, there is a need for the design and development of new alloys that are intrinsically low-cost and lend themselves to fabrication by novel cost-effective net shape processing. The approaches that might be used to select, design and process both conventional alloys and novel alloy systems will be reviewed, with a focus on innovation in design of low-cost alloys amenable to new processing paths and increasingly tolerant of variability in composition.

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

scholarly journals Facile Synthesis of Coral Reef-Like ZnO/CoS2 Nanostructure on Nickel Foam as an Advanced Electrode Material for High-Performance Supercapacitors

Energies ◽  
2021 ◽  
Vol 14 (16) ◽  
pp. 4925
Author(s):  
Ikkurthi Kanaka Durga ◽  
Kummara Venkata Guru Raghavendra ◽  
Naga Bhushanam Kundakarla ◽  
Suresh Alapati ◽  
Jin-Woo Ahn ◽  
...  
Keyword(s):  
High Performance ◽  
Nickel Foam ◽  
Specific Capacity ◽  
Cost Effective ◽  
X Ray Diffraction ◽  
Hydrothermal Route ◽  
Binder Free ◽  
Crystalline Nature ◽  
The Cost ◽  
Morphology Of Surface

Nanocomposite electrodes receive much attention because of their excellent energy storage nature. Electrodes for supercapacitors have come a major source of interest. In this pursuit, the current work elucidates binder-free coral reefs resembling ZnO/CoS2 nanoarchitectures synthesized on the surface of Ni foams employing the cost-effective hydrothermal route. The Zno/CoS2 nanocomposite demonstrated excellent battery-type behavior, which can be employed for supercapcitor application. Various analyses were carried out in the current study, such as X-ray diffraction and high-resolution scanning electron microscopy, which allowed defining the crystalline nature and morphology of surface with ZnO/CoS2 nanoarchitectures. Electrochemical measures such as cyclic voltammetry, galvanostatic charge discharge, and potentiostatic impedance spectroscopy confirmed the battery-type behavior of the material. The synthesized precursors of binder-free ZnO/CoS2 nanostructures depicted an excellent specific capacity of 400.25 C·g−1 at 1 A·g−1, with a predominant cycling capacity of 88. 2% and retention holding of 68% at 10 A·g−1 and 2 A·g−1, even after 4000 cycles, representing an improvement compared to the pristine ZnO and CoS2 electroactive materials. Therefore, the electrochemical and morphological analyses suggest the excellent behavior of the ZnO/CoS2 nanoarchitectures, making them promising for supercapacitors.

scholarly journals Ultra-high speed reconfigurable microwave and radio frequency photonic intensity differentiators using Kerr frequency optical microcombs

2021 ◽  
Author(s):  
David Moss
Keyword(s):  
Radio Frequency ◽  
High Speed ◽  
High Performance ◽  
Third Order ◽  
Transversal Filter ◽  
Multi Wavelength ◽  
Gaussian Input ◽  
On Chip ◽  
The Cost ◽  
Good Agreement

Abstract We propose and experimentally demonstrate a microwave photonic intensity differentiator based on a Kerr optical comb generated by a compact integrated micro-ring resonator (MRR). The on-chip Kerr optical comb, containing a large number of comb lines, serves as a high-performance multi-wavelength source for the transversal filter, which will greatly reduce the cost, size, and complexity of the system. Moreover, owing to the compactness of the integrated MRR, up to 200-GHz frequency spacing of the Kerr optical comb can be achieved, enabling a potential operation bandwidth of over 100 GHz. By programming and shaping individual comb lines according to the calculated tap weights, a reconfigurable intensity differentiator with variable differentiation orders can be realized. The operation principle is theoretically analyzed, and experimental demonstrations of first-order, second-order, and third-order differentiation functions based on the principle are presented. The radio frequency (RF) amplitude and phase responses of multi-order intensity differentiations are characterized, and system demonstrations of real-time differentiations for Gaussian input signal are also performed. The experimental results show good agreement with theory, confirming the effectiveness of our approach.

scholarly journals Micro–Macro: Selective Integration of Microfeatures Inside Low-Cost Macromolds for PDMS Microfluidics Fabrication

Micromachines ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 576 ◽  
Author(s):  
Edgar Jiménez-Díaz ◽  
Mariel Cano-Jorge ◽  
Diego Zamarrón-Hernández ◽  
Lucia Cabriales ◽  
Francisco Páez-Larios ◽  
...  
Keyword(s):  
Soft Lithography ◽  
Low Cost ◽  
Cost Effective ◽  
Microfluidic Chips ◽  
Single Chip ◽  
Lab On Chip ◽  
Molding Method ◽  
On Chip ◽  
Selective Integration ◽  
Important Progress

Microfluidics has become a very promising technology in recent years, due to its great potential to revolutionize life-science solutions. Generic microfabrication processes have been progressively made available to academic laboratories thanks to cost-effective soft-lithography techniques and enabled important progress in applications like lab-on-chip platforms using rapid- prototyping. However, micron-sized features are required in most designs, especially in biomimetic cell culture platforms, imposing elevated costs of production associated with lithography and limiting the use of such devices. In most cases, however, only a small portion of the structures require high-resolution and cost may be decreased. In this work, we present a replica-molding method separating the fabrication steps of low (macro) and high (micro) resolutions and then merging the two scales in a single chip. The method consists of fabricating the largest possible area in inexpensive macromolds using simple techniques such as plastics micromilling, laser microfabrication, or even by shrinking printed polystyrene sheets. The microfeatures were made on a separated mold or onto existing macromolds using photolithography or 2-photon lithography. By limiting the expensive area to the essential, the time and cost of fabrication can be reduced. Polydimethylsiloxane (PDMS) microfluidic chips were successfully fabricated from the constructed molds and tested to validate our micro–macro method.

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