Advances in WLCSP Technologies to Enable Cost Reduction

2010 ◽  
Vol 7 (3) ◽  
pp. 160-163 ◽  
Author(s):  
R. Chilukuri ◽  
R. Anderson ◽  
B. Rogers ◽  
A. Syed
Keyword(s):  
Cycle Time ◽  
Cost Reduction ◽  
Failure Modes ◽  
Solder Alloys ◽  
Product Introduction ◽  
Reliability Data ◽  
Package Size ◽  
Capital Depreciation ◽  
Board Level ◽  
Board Level Reliability

This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows (CSPX3 and CSPX2). This paper examines material options for these structures, with a focus on the redistribution layer and solder alloys. Package level and board level reliability data along with a description of the failure modes are presented.

Advances in WLCSP Technologies to Enable Cost-Reduction

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002291-002311
Author(s):  
Rex Anderson ◽  
R. Chilukuri ◽  
B. Rogers ◽  
A. Syed
Keyword(s):  
Cycle Time ◽  
Cost Reduction ◽  
Business Models ◽  
Failure Modes ◽  
Time Pressure ◽  
Semiconductor Industry ◽  
Product Reliability ◽  
Product Introduction ◽  
Silicon Technology ◽  
Technology Nodes

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

scholarly journals Improved Reliability and Mechanical Performance of Sn58Bi Solder Alloys

2019 ◽  
Author(s):  
Guang Ren ◽  
Maurice N. Collins
Keyword(s):  
Mechanical Properties ◽  
Mechanical Performance ◽  
Temperature Cycling ◽  
Time To Failure ◽  
Solder Alloys ◽  
Hardening Mechanism ◽  
Solder Microstructure ◽  
Board Level ◽  
Board Level Reliability ◽  
Ag3sn Imcs

Abstract: Microstructural and mechanical properties of the eutectic Sn58Bi and micro-alloyed Sn57.6Bi0.4Ag solder alloys were compared. With the addition of Ag micro-alloy, the tensile strength was improved and this is attributed to a combination of microstructure refinement and an Ag3Sn precipitation hardening mechanism. However, ductility is slightly deteriorated due to the brittle nature of the Ag3Sn intermetallic compounds (IMCs). Additionally, a board level reliability study of Ag micro-alloyed Sn58Bi solder joints produced utilising a surface-mount technology (SMT) process, were assessed under accelerated temperature cycling (ATC) conditions. Results reveal that micro-alloyed Sn57.6Bi0.4Ag has a higher characteristic lifetime with a narrower failure distribution. This enhanced reliability corresponds with improved bulk mechanical properties. It is postulated that Ag3Sn IMCs are located at the Sn-Bi phase boundaries and suppress the solder microstructure from coarsening during the temperature cycling, hereby extending the time to failure.

scholarly journals Improved Reliability and Mechanical Performance of Ag Microalloyed Sn58Bi Solder Alloys

Metals ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 462 ◽  
Author(s):  
Guang Ren ◽  
Maurice N. Collins
Keyword(s):  
Mechanical Properties ◽  
Mechanical Performance ◽  
Temperature Cycling ◽  
Time To Failure ◽  
Solder Alloys ◽  
Hardening Mechanism ◽  
Solder Microstructure ◽  
Free Solder ◽  
Board Level ◽  
Board Level Reliability

Ag microalloyed Sn58Bi has been investigated in this study as a Pb-free solder candidate to be used in modern electronics industry in order to cope with the increasing demands for low temperature soldering. Microstructural and mechanical properties of the eutectic Sn58Bi and microalloyed Sn57.6Bi0.4Ag solder alloys were compared. With the addition of Ag microalloy, the tensile strength was improved, and this was attributed to a combination of microstructure refinement and an Ag3Sn precipitation hardening mechanism. However, ductility was slightly deteriorated due to the brittle nature of the Ag3Sn intermetallic compounds (IMCs). Additionally, a board level reliability study of Ag microalloyed Sn58Bi solder joints produced utilizing a surface-mount technology (SMT) process, were assessed under accelerated temperature cycling (ATC) conditions. Results revealed that microalloyed Sn57.6Bi0.4Ag had a higher characteristic lifetime with a narrower failure distribution. This enhanced reliability corresponds with improved bulk mechanical properties. It is postulated that Ag3Sn IMCs are located at the Sn–Bi phase boundaries and suppress the solder microstructure from coarsening during the temperature cycling, hereby extending the time to failure.

Board Level Reliability of Automotive Grade WLCSP for Radar Applications

2020 ◽  
Author(s):  
Nishant Lakhera ◽  
Burt Carpenter ◽  
Trung Duong ◽  
Mollie Benson ◽  
Andrew J Mawer
Keyword(s):  
Radar Applications ◽  
Board Level ◽  
Board Level Reliability

Board-Level Reliability of Pb-Free Surface Mounted Assemblies during Thermal Shock Testing

2006 ◽  
Vol 15-17 ◽  
pp. 633-638 ◽  
Author(s):  
Jong Woong Kim ◽  
Hyun Suk Chun ◽  
Sang Su Ha ◽  
Jong Hyuck Chae ◽  
Jin Ho Joo ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Solder Joints ◽  
Lead Frame ◽  
Shear Forces ◽  
Microstructural Investigation ◽  
Shock Testing ◽  
Ceramic Capacitor ◽  
Board Level ◽  
Board Level Reliability ◽  
Thermal Shocks

Board-level reliability of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu solder joints was evaluated using thermal shock testing. In the microstructural investigation of the solder joints, the formation of Cu6Sn5 intermetallic compound (IMC) layer was observed between both solders and Cu lead frame, but any crack or newly introduced defect cannot be found even after 2000 cycles of thermal shocks. Shear test of the multi layer ceramic capacitor (MLCC) joints were also conducted to investigate the effect of microstructural variations on the bonding strength of the solder joints. Shear forces of the both solder joints decreased with increasing thermal shock cycles. The reason to the decrease in shear force was discussed with fracture surfaces of the shear tested solder joints.

A Dynamic Bending Method for PoP Package Board Level Reliability Validation

2018 ◽  
Author(s):  
Jeffrey Lee ◽  
Cheng-Chih Chen ◽  
Lane Brown ◽  
Esme Mehretu ◽  
Thomas Obrien ◽  
...  
Keyword(s):  
Dynamic Bending ◽  
Board Level ◽  
Board Level Reliability

Board Level Reliability of Solder Joint with a Low CTE PCB

2019 ◽  
Vol 44 (1) ◽  
pp. 975-983 ◽  
Author(s):  
Kyoungmoo Harr ◽  
Chang-Bae Lee ◽  
Yoon-Su Kim ◽  
Seungwook Park ◽  
Jin-Gu Kim ◽  
...  
Keyword(s):  
Solder Joint ◽  
Board Level ◽  
Board Level Reliability
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