A Dynamic Bending Method for PoP Package Board Level Reliability Validation

2018 ◽  
Author(s):  
Jeffrey Lee ◽  
Cheng-Chih Chen ◽  
Lane Brown ◽  
Esme Mehretu ◽  
Thomas Obrien ◽  
...  
Keyword(s):  
Dynamic Bending ◽  
Board Level ◽  
Board Level Reliability

Board Level Reliability of Automotive Grade WLCSP for Radar Applications

2020 ◽  
Author(s):  
Nishant Lakhera ◽  
Burt Carpenter ◽  
Trung Duong ◽  
Mollie Benson ◽  
Andrew J Mawer
Keyword(s):  
Radar Applications ◽  
Board Level ◽  
Board Level Reliability

Board-Level Reliability of Pb-Free Surface Mounted Assemblies during Thermal Shock Testing

2006 ◽  
Vol 15-17 ◽  
pp. 633-638 ◽  
Author(s):  
Jong Woong Kim ◽  
Hyun Suk Chun ◽  
Sang Su Ha ◽  
Jong Hyuck Chae ◽  
Jin Ho Joo ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Solder Joints ◽  
Lead Frame ◽  
Shear Forces ◽  
Microstructural Investigation ◽  
Shock Testing ◽  
Ceramic Capacitor ◽  
Board Level ◽  
Board Level Reliability ◽  
Thermal Shocks

Board-level reliability of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu solder joints was evaluated using thermal shock testing. In the microstructural investigation of the solder joints, the formation of Cu6Sn5 intermetallic compound (IMC) layer was observed between both solders and Cu lead frame, but any crack or newly introduced defect cannot be found even after 2000 cycles of thermal shocks. Shear test of the multi layer ceramic capacitor (MLCC) joints were also conducted to investigate the effect of microstructural variations on the bonding strength of the solder joints. Shear forces of the both solder joints decreased with increasing thermal shock cycles. The reason to the decrease in shear force was discussed with fracture surfaces of the shear tested solder joints.

Board Level Reliability of Solder Joint with a Low CTE PCB

2019 ◽  
Vol 44 (1) ◽  
pp. 975-983 ◽  
Author(s):  
Kyoungmoo Harr ◽  
Chang-Bae Lee ◽  
Yoon-Su Kim ◽  
Seungwook Park ◽  
Jin-Gu Kim ◽  
...  
Keyword(s):  
Solder Joint ◽  
Board Level ◽  
Board Level Reliability

PoP Technology for the Automotive Industry

2014 ◽  
Vol 2014 (1) ◽  
pp. 000081-000085
Author(s):  
Jaimal Williamson ◽  
Kurt Wachtler ◽  
David Chin ◽  
Mike Pierce
Keyword(s):  
Automotive Industry ◽  
Memory Performance ◽  
Automotive Applications ◽  
Defect Level ◽  
Packaging Technology ◽  
Package Design ◽  
Surface Mount ◽  
Board Level ◽  
Performance Surface ◽  
Board Level Reliability

Package-on-Package (PoP) technology has been in production for commercial and portable electronic applications for many years. The key challenge for PoP in automotive applications is meeting the aggressive defect level requirements. The need for PoP has historically been driven by mobile and tablet applications and an increased demand for more processor and memory performance within smaller spaces. With the maturity and excellent historical performance of PoP technology used with TI OMAPTM processor products, PoP can now be introduced as a reliable packaging technology in the automotive industry. This paper will describe the work involved in the enablement of commercial PoP technology into the automotive industry. The challenges and requirements regarding package design, warpage performance, surface mount (SMT) characterization, and board-level reliability (BLR) performance will all be explained.

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