Proven Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002399-002427
Author(s):  
Kimberly D. Pollard ◽  
Nichelle Gilbert ◽  
Don Pfettscher ◽  
Spencer Hochstetler
Keyword(s):  
Solder Bump ◽  
Surface Preparation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Aspect Ratios ◽  
Advanced Packaging ◽  
Free Solder ◽  
Cleaning Technology ◽  
Micro Pillars

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success. In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

The Effects of Temperature Cyclic Loading on Lead-Free Solder Joints of Wafer Level Chip Scale Package by Taguchi Method

2008 ◽  
Vol 130 (1) ◽  
Author(s):  
Wen-Ren Jong ◽  
Hsin-Chun Tsai ◽  
Hsiu-Tao Chang ◽  
Shu-Hui Peng
Keyword(s):  
Low Temperature ◽  
Shear Strain ◽  
Solder Joints ◽  
Strain Range ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Free Solder ◽  
Plastic Creep

In this study, the effects of the temperature cyclic loading on three lead-free solder joints of 96.5Sn–3.5Ag, 95.5Sn–3.8Ag-0.7Cu, and 95.5Sn–3.9Ag-0.6Cu bumped wafer level chip scale package (WLCSP) on printed circuit board assemblies are investigated by Taguchi method. The orthogonal arrays of L16 is applied to examine the shear strain effects of solder joints under five temperature loading parameters of the temperature ramp rate, the high and low temperature dwells, and the dwell time of both high and low temperatures by means of three simulated analyses of creep, plastic, and plastic-creep behavior on the WLCSP assemblies. It is found that the temperature dwell is the most significant factor on the effects of shear strain range from these analyses. The effect of high temperature dwell on the shear strain range is larger than that of low temperature dwell in creep analysis, while the effect of high temperature dwell on the shear strain range is smaller than that of low temperature dwell in both plastic and plastic-creep analyses.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2000 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

Abstract In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.

Reliability Modeling of Lead Free Solder Joints in Wafer-Level Chip Scale Packages

2007 ◽  
Author(s):  
Jie-Hua Zhao ◽  
Vikas Gupta ◽  
Alok Lohia ◽  
Darvin Edwards
Keyword(s):  
Solder Joints ◽  
Inelastic Strain ◽  
Constitutive Laws ◽  
Constitutive Law ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Reliability Modeling ◽  
Correlation Parameters ◽  
Free Solder

Board level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSP’s) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep and time hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared to experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.

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