From C4 to micro-bump: Adapting lead free solder electroplating processes to next-gen advanced packaging applications

Author(s):  
Julia Woertink ◽  
Yi Qin ◽  
Jonathan Prange ◽  
Pedro Lopez-Montesinos ◽  
Inho Lee ◽  
...  
2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002399-002427
Author(s):  
Kimberly D. Pollard ◽  
Nichelle Gilbert ◽  
Don Pfettscher ◽  
Spencer Hochstetler

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success. In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.


2015 ◽  
Vol 10 (1) ◽  
pp. 2641-2648
Author(s):  
Rizk Mostafa Shalaby ◽  
Mohamed Munther ◽  
Abu-Bakr Al-Bidawi ◽  
Mustafa Kamal

The greatest advantage of Sn-Zn eutectic is its low melting point (198 oC) which is close to the melting point. of Sn-Pb eutectic solder (183 oC), as well as its low price per mass unit compared with Sn-Ag and Sn-Ag-Cu solders. In this paper, the effect of 0.0, 1.0, 2.0, 3.0, 4.0, and 5.0 wt. % Al as ternary additions on melting temperature, microstructure, microhardness and mechanical properties of the Sn-9Zn lead-free solders were investigated. It is shown that the alloying additions of Al at 4 wt. % to the Sn-Zn binary system lead to lower of the melting point to 195.72 ˚C.  From x-ray diffraction analysis, an aluminium phase, designated α-Al is detected for 4 and 5 wt. % Al compositions. The formation of an aluminium phase causes a pronounced increase in the electrical resistivity and microhardness. The ternary Sn-9Zn-2 wt.%Al exhibits micro hardness superior to Sn-9Zn binary alloy. The better Vickers hardness and melting points of the ternary alloy is attributed to solid solution effect, grain size refinement and precipitation of Al and Zn in the Sn matrix.  The Sn-9%Zn-4%Al alloy is a lead-free solder designed for possible drop-in replacement of Pb-Sn solders.  


2021 ◽  
Author(s):  
M. N. Ervina Efzan ◽  
M. M. Nur Haslinda ◽  
M. M. Al Bakri Abdullah

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