scholarly journals Robust Pressure Sensor in SOI Technology with Butterfly Wiring for Airfoil Integration

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6140
Author(s):  
Jan Niklas Haus ◽  
Martin Schwerter ◽  
Michael Schneider ◽  
Marcel Gäding ◽  
Monika Leester-Schädel ◽  
...  

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV−1 bar−1. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors.

1998 ◽  
Vol 544 ◽  
Author(s):  
J. E. Klemberg-Sapieha ◽  
L. Martinu ◽  
N. L. S. Yamasaki ◽  
C. W. Lantman

AbstractAdhesion of plasma-deposited optical and protective coatings, such as amorphous hydrogenated silicon nitride, SiN1.3, on polymethyl-methacrylate (PMMA) substrates has been found to be limited by a cohesive failure inside the PMMA bulk. Using direct exposure to a low pressure plasma in helium or to vacuum ultraviolet radiation generated from H2 plasma for an extended period of time, we succeeded to obtain excellent adhesion even under a humidity test at elevated temperature. We found, using a multitechnique approach, that such improved adhesion is achieved by forming a crosslinked, mechanically stabilized layer in the interfacial region, which possesses a physical thickness of 50 to 100 nm.


2019 ◽  
Vol 2019 (1) ◽  
pp. 000169-000175
Author(s):  
Christian Klewer ◽  
Frank Kuechenmeister ◽  
Jens Paul ◽  
Dirk Breuer ◽  
Bjoern Boehme ◽  
...  

Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000033-000043 ◽  
Author(s):  
Tao WANG ◽  
Jian CAI ◽  
Qian WANG ◽  
Hao ZHANG ◽  
Zheyao WANG

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.


1993 ◽  
Vol 164-166 ◽  
pp. 235-238 ◽  
Author(s):  
O. Klíma ◽  
O. Štika ◽  
Ho Tha Ha ◽  
S. Fouad Abdel Hamied ◽  
J. Stuchlík ◽  
...  

1998 ◽  
Vol 1 (2) ◽  
pp. 81-85
Author(s):  
Clara EE Hanekamp ◽  
Hans JRM Bonnier ◽  
Rolf H Michels ◽  
Kathinka H Peels ◽  
Eric PCM Heijmen ◽  
...  

1996 ◽  
Vol 43 (9) ◽  
pp. 1592-1601 ◽  
Author(s):  
S.J. Bijlsma ◽  
H. van Kranenburg ◽  
K.J.B.M. Nieuwesteeg ◽  
M.G. Pitt ◽  
J.F. Verweij

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