scholarly journals Remarkable Stability Improvement of ZnO TFT with Al2O3 Gate Insulator by Yttrium Passivation with Spray Pyrolysis

Nanomaterials ◽  
2020 ◽  
Vol 10 (5) ◽  
pp. 976 ◽  
Author(s):  
Jewel Kumer Saha ◽  
Ravindra Naik Bukke ◽  
Narendra Naik Mude ◽  
Jin Jang
Keyword(s):  
Spray Pyrolysis ◽  
Threshold Voltage ◽  
Moisture Absorption ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
Zno Films ◽  
Threshold Voltage Shift ◽  
Bias Temperature Stress ◽  
The Stability ◽  
The Impact

We report the impact of yttrium oxide (YOx) passivation on the zinc oxide (ZnO) thin film transistor (TFT) based on Al2O3 gate insulator (GI). The YOx and ZnO films are both deposited by spray pyrolysis at 400 and 350 °C, respectively. The YOx passivated ZnO TFT exhibits high device performance of field effect mobility (μFE) of 35.36 cm2/Vs, threshold voltage (VTH) of 0.49 V and subthreshold swing (SS) of 128.4 mV/dec. The ZnO TFT also exhibits excellent device stabilities, such as negligible threshold voltage shift (∆VTH) of 0.15 V under positive bias temperature stress and zero hysteresis voltage (VH) of ~0 V. YOx protects the channel layer from moisture absorption. On the other hand, the unpassivated ZnO TFT with Al2O3 GI showed inferior bias stability with a high SS when compared to the passivated one. It is found by XPS that Y diffuses into the GI interface, which can reduce the interfacial defects and eliminate the hysteresis of the transfer curve. The improvement of the stability is mainly due to the diffusion of Y into ZnO as well as the ZnO/Al2O3 interface.

scholarly journals Hysteresis Reduction for Organic Thin Film Transistors with Multiple Stacked Functional Zirconia Polymeric Films

Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 634 ◽  
Author(s):  
Kwon ◽  
Choi ◽  
Bae ◽  
Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Polymeric Films ◽  
Gate Insulator ◽  
Organic Thin Film ◽  
Threshold Voltage Shift ◽  
Gate Insulators ◽  
Temperature Solution

We show that transfer hysteresis for a pentacene thin film transistor (TFT) with a low-temperature solution-processed zirconia (ZrOx) gate insulator can be remarkably reduced by modifying the ZrOx surface with a thin layer of crosslinked poly(4-vinylphenol) (c-PVP). Pentacene TFTs with bare ZrOx and c-PVP stacked ZrOx gate insulators were fabricated, and their hysteresis behaviors compared. The different gate insulators exhibited no significant surface morphology or capacitance differences. The threshold voltage shift magnitude decreased by approximately 71% for the TFT with the c-PVP stacked ZrOx gate insulator compared with the bare ZrOx gate insulator, with 0.75 ± 0.05 and 0.22 ± 0.03 V threshold voltage shifts for the bare ZrOx and c-PVP stacked ZrOx gate insulators, respectively. The hysteresis reduction was attributed to effectively covering hysteresis-inducing charge trapping sites on ZrOx surfaces.

Impact of Nitric Oxide Post Oxidation Anneal on the Bias Temperature Instability and the On-Resistance of 4H-SiC nMOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 709-712 ◽  
Author(s):  
Gerald Rescher ◽  
Gregor Pobegen ◽  
Thomas Aichinger
Keyword(s):  
Nitric Oxide ◽  
Electric Field ◽  
Temperature Stress ◽  
Threshold Voltage ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Bias Temperature Instability ◽  
Bias Temperature Stress ◽  
The Impact ◽  
Stress Voltage

We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance Ron of n-channel MOSFETs and on the threshold voltage shift ∆Vth following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆Vth for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆Vth, the device Ron increases with NO POA temperature and time.

Origin of threshold voltage shift by interfacial trap density in amorphous InGaZnO thin film transistor under temperature induced stress

2011 ◽  
Vol 99 (6) ◽  
pp. 062108 ◽  
Author(s):  
Bosul Kim ◽  
Eugene Chong ◽  
Do Hyung Kim ◽  
Yong Woo Jeon ◽  
Dae Hwan Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Trap Density ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Induced Stress ◽  
Amorphous Ingazno

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

scholarly journals Negative threshold voltage shift in an a-IGZO thin film transistor under X-ray irradiation

RSC Advances ◽  
2019 ◽  
Vol 9 (36) ◽  
pp. 20865-20870 ◽  
Author(s):  
Dong-Gyu Kim ◽  
Jong-Un Kim ◽  
Jun-Sun Lee ◽  
Kwon-Shik Park ◽  
Youn-Gyoung Chang ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Hydrogen Incorporation ◽  
X Ray ◽  
Spectroscopic Analyses ◽  
Bottom Gate ◽  
Igzo Tft

We studied the effect of X-ray irradiation on the negative threshold voltage shift of bottom-gate a-IGZO TFT. Based on spectroscopic analyses, we found that this behavior was caused by hydrogen incorporation and oxygen vacancy ionization.

COMPARATIVE INSTABILITIES ANALYSIS FOR a-Si:H BODY-TIED TFT (BT-TFT) AND FLOATING BODY TFT (FB-TFT) UNDER BIAS TEMPERATURE STRESSING (BTS)

2008 ◽  
Vol 22 (05) ◽  
pp. 337-341
Author(s):  
YONG K. LEE ◽  
SUNG-HOON CHOA
Keyword(s):  
Silicon Nitride ◽  
Threshold Voltage ◽  
Gate Insulator ◽  
Floating Body ◽  
Negative Bias ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Hole Trapping

The a- Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with negative and positive bias to realize the instability mechanisms. With proposed BT-TFT and FB-TFT devices, it is found that the threshold voltages of both BT-TFT and BT-TFT devices are positively shifted under positive bias stress and then negatively shifted for negative bias stress. The positive threshold voltage shift is due to the electron trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The negative threshold voltage shift is mainly due to hole trapping and/or electron de-trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The positive or negative threshold voltage shift keeps increasing with increasing positive or negative gate bias for both BT-TFT and FB-TFT devices. However, as far as the threshold voltage shift slope is concerned, under positive bias stress, both BT-TFT and FB-TFT devices are similar to each other. On the other hand, under negative bias stress, BT-TFT shift amount is much less than one for the FB-TFT device.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

Performance of ZnO TFTs with AlN as Insulator

2007 ◽  
Vol 1035 ◽  
Author(s):  
Maria Merlyne De Souza ◽  
Richard B Cross ◽  
Suhas Jejurikar ◽  
K P Adhi
Keyword(s):  
Surface Roughness ◽  
Threshold Voltage ◽  
Rf Sputtering ◽  
Interface States ◽  
Aluminium Nitride ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
The Stability

AbstractThe performance of ZnO TFTs fabricated via RF sputtering, with Aluminium Nitride (AlN) as the underlying insulator are reported. The surface roughness of ZnO with AlN is lower than that with SiN by at least 5 times, and that with SiO2 by 30 times. The resulting mobility for the three insulators AlN, SiN, SiO2 using identical process is found to be 3, 0.2-0.7 and 0.1-0.25 cm2/Vs respectively. There does not appear to be any corresponding improvement in the stability of the AlN devices. The devices demonstrate significant positive threshold voltage shift with positive gate bias and negative threshold voltage shift with negative gate bias. The underlying cause is surmised to be ultra-fast interface states in combination with bulk traps in the ZnO.

Sign in / Sign up

Export Citation Format

Share Document