scholarly journals A Comparative Study of E-Beam Deposited Gate Dielectrics on Channel Width-Dependent Performance and Reliability of a-IGZO Thin-Film Transistors

Materials ◽  
2018 ◽  
Vol 11 (12) ◽  
pp. 2502 ◽  
Author(s):  
Gwomei Wu ◽  
Anup Sahoo ◽  
Dave Chen ◽  
J. Chang
Keyword(s):  
Thin Film ◽  
Comparative Study ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Width ◽  
Capacitance Density ◽  
Voltage Variation ◽  
Igzo Tft

A comparative study on the effects of e-beam deposited gate dielectrics for amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) has been carried out using SiO2, Si3N4, and Ta2O5 dielectric materials. The channel width dependent device electrical performances were investigated using three different sizes of 500 μm, 1000 μm, and 1500 μm. The reliability characteristics were revealed by the threshold voltage variation and drain current variation under positive bias stress. The e-beam deposited high-k dielectric Ta2O5 exhibited the highest stability at the stress voltage of 3 V for 1000 s due to its high capacitance density at 34.1 nF/cm2. The threshold voltage variation along the channel width decreased from SiO2, then Si3N4, to Ta2O5, because of the increased insulating property and density of capacitance. The SiO2-based a-IGZO TFT achieved a high field effect mobility of 27.9 cm2/V·s and on–off current ratio > 107 at the lower channel width of 500 μm. The gate leakage current also decreased with increasing the channel width/length ratio. In addition, the SiO2 gate dielectric-based a-IGZO TFT could be a faster device, whereas the Ta2O5 gate dielectric would be a good candidate for a higher reliability component with adequate surface treatment.

High-Performance Damascene-Gate Thin Film Transistors

1999 ◽  
Vol 557 ◽  
Author(s):  
Eugene Ma ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
High Performance ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Linear Region ◽  
Threshold Voltages ◽  
Bottom Gate

AbstractWe report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNX gate dielectrics as thin as 50 nm. Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, ION/IOFF current ratios of 106 and linear region field-effect mobilities of 0.6 cm2/Vs.

Investigation of channel width-dependent threshold voltage variation in a-InGaZnO thin-film transistors

2014 ◽  
Vol 104 (13) ◽  
pp. 133503 ◽  
Author(s):  
Kuan-Hsien Liu ◽  
Ting-Chang Chang ◽  
Ming-Siou Wu ◽  
Yi-Syuan Hung ◽  
Pei-Hua Hung ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Channel Width ◽  
Voltage Variation

Comparative study on extraction methods of threshold voltage for thin‐film transistors

2019 ◽  
Vol 27 (12) ◽  
pp. 816-821
Author(s):  
Ziheng Bai ◽  
Xuewen Shi ◽  
Jiawei Wang ◽  
Nianduan Lu ◽  
Xinlv Duan ◽  
...  
Keyword(s):  
Thin Film ◽  
Comparative Study ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Extraction Methods

Comparative study of electrical instabilities in InGaZnO thin film transistors with gate dielectrics

2012 ◽  
Vol 52 (9-10) ◽  
pp. 2504-2507 ◽  
Author(s):  
Seul Ki Lee ◽  
Sung Il Hong ◽  
Yeon Ho Lee ◽  
Se Won Lee ◽  
Won Ju Cho ◽  
...  
Keyword(s):  
Thin Film ◽  
Comparative Study ◽  
Thin Film Transistors ◽  
Gate Dielectrics

scholarly journals Optimizing the Properties of InGaZnOx Thin Film Transistors by Adjusting the Adsorbed Degree of Cs+ Ions

Materials ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2300
Author(s):  
He Zhang ◽  
Yaogong Wang ◽  
Ruozheng Wang ◽  
Xiaoning Zhang ◽  
Chunliang Liu
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Carrier Mobility ◽  
Oxygen Vacancies ◽  
Immersion Method ◽  
Bias Stress ◽  
Cs Ions ◽  
Transfer Properties ◽  
Igzo Tft

To improve the performance of amorphous InGaZnOx (a-IGZO) thin film transistors (TFTs), in this thesis, Cs+ ions adsorbed IGZO (Cs-IGZO) films were prepared through a solution immersion method at low temperature. Under the modification of surface structure and oxygen vacancies concentrations of a-IGZO film, with the effective introduction of Cs+ ions into the surface of a-IGZO films, the transfer properties and stability of a-IGZO TFTs are greatly improved. Different parameters of Cs+ ion concentrations were investigated in our work. When the Cs+ ions concentration reached 2% mol/L, the optimized performance Cs-IGZO TFT was obtained, showing the carrier mobility of 18.7 cm2 V−1 s−1, the OFF current of 0.8 × 10−10 A, and the threshold voltage of 0.2 V, accompanied by the threshold voltage shifts of 1.3 V under positive bias stress for 5000 s.

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

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