High-Performance Damascene-Gate Thin Film Transistors

1999 ◽  
Vol 557 ◽  
Author(s):  
Eugene Ma ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
High Performance ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Linear Region ◽  
Threshold Voltages ◽  
Bottom Gate

AbstractWe report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNX gate dielectrics as thin as 50 nm. Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, ION/IOFF current ratios of 106 and linear region field-effect mobilities of 0.6 cm2/Vs.

Two-dimensional organic–inorganic hybrid perovskite field-effect transistors with polymers as bottom-gate dielectrics

2019 ◽  
Vol 7 (14) ◽  
pp. 4004-4012 ◽  
Author(s):  
Fan Zhang ◽  
Huaye Zhang ◽  
Lijie Zhu ◽  
Liang Qin ◽  
Yue Wang ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Two Dimensional ◽  
Inorganic Hybrid ◽  
Dielectric Layers ◽  
Hybrid Perovskite ◽  
Bottom Gate

High-performance bottom-gate 2D-layered (PEA)2SnI4 field-effect transistors have been fabricated using PVA/CL-PVP as gate dielectric layers.

scholarly journals A Comparative Study of E-Beam Deposited Gate Dielectrics on Channel Width-Dependent Performance and Reliability of a-IGZO Thin-Film Transistors

Materials ◽  
2018 ◽  
Vol 11 (12) ◽  
pp. 2502 ◽  
Author(s):  
Gwomei Wu ◽  
Anup Sahoo ◽  
Dave Chen ◽  
J. Chang
Keyword(s):  
Thin Film ◽  
Comparative Study ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Width ◽  
Capacitance Density ◽  
Voltage Variation ◽  
Igzo Tft

A comparative study on the effects of e-beam deposited gate dielectrics for amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) has been carried out using SiO2, Si3N4, and Ta2O5 dielectric materials. The channel width dependent device electrical performances were investigated using three different sizes of 500 μm, 1000 μm, and 1500 μm. The reliability characteristics were revealed by the threshold voltage variation and drain current variation under positive bias stress. The e-beam deposited high-k dielectric Ta2O5 exhibited the highest stability at the stress voltage of 3 V for 1000 s due to its high capacitance density at 34.1 nF/cm2. The threshold voltage variation along the channel width decreased from SiO2, then Si3N4, to Ta2O5, because of the increased insulating property and density of capacitance. The SiO2-based a-IGZO TFT achieved a high field effect mobility of 27.9 cm2/V·s and on–off current ratio > 107 at the lower channel width of 500 μm. The gate leakage current also decreased with increasing the channel width/length ratio. In addition, the SiO2 gate dielectric-based a-IGZO TFT could be a faster device, whereas the Ta2O5 gate dielectric would be a good candidate for a higher reliability component with adequate surface treatment.

scholarly journals Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Oxygen Content ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electron Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Drain Side ◽  
Bottom Gate

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

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