Comparative study on extraction methods of threshold voltage for thin‐film transistors

2019 ◽  
Vol 27 (12) ◽  
pp. 816-821
Author(s):  
Ziheng Bai ◽  
Xuewen Shi ◽  
Jiawei Wang ◽  
Nianduan Lu ◽  
Xinlv Duan ◽  
...  
Materials ◽  
2018 ◽  
Vol 11 (12) ◽  
pp. 2502 ◽  
Author(s):  
Gwomei Wu ◽  
Anup Sahoo ◽  
Dave Chen ◽  
J. Chang

A comparative study on the effects of e-beam deposited gate dielectrics for amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) has been carried out using SiO2, Si3N4, and Ta2O5 dielectric materials. The channel width dependent device electrical performances were investigated using three different sizes of 500 μm, 1000 μm, and 1500 μm. The reliability characteristics were revealed by the threshold voltage variation and drain current variation under positive bias stress. The e-beam deposited high-k dielectric Ta2O5 exhibited the highest stability at the stress voltage of 3 V for 1000 s due to its high capacitance density at 34.1 nF/cm2. The threshold voltage variation along the channel width decreased from SiO2, then Si3N4, to Ta2O5, because of the increased insulating property and density of capacitance. The SiO2-based a-IGZO TFT achieved a high field effect mobility of 27.9 cm2/V·s and on–off current ratio > 107 at the lower channel width of 500 μm. The gate leakage current also decreased with increasing the channel width/length ratio. In addition, the SiO2 gate dielectric-based a-IGZO TFT could be a faster device, whereas the Ta2O5 gate dielectric would be a good candidate for a higher reliability component with adequate surface treatment.


Author(s):  
Benjamin King ◽  
Andrew J. Daszczynski ◽  
Nicole A. Rice ◽  
Alexander J. Peltekoff ◽  
Nathan J. Yutronkie ◽  
...  

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.


2000 ◽  
Vol 76 (17) ◽  
pp. 2442-2444 ◽  
Author(s):  
C. T. Angelis ◽  
C. A. Dimitriadis ◽  
F. V. Farmakis ◽  
J. Brini ◽  
G. Kamarinos ◽  
...  

2016 ◽  
Vol 3 (24) ◽  
pp. 1600713 ◽  
Author(s):  
Ji Hoon Park ◽  
Fwzah H. Alshammari ◽  
Zhenwei Wang ◽  
Husam N. Alshareef

2013 ◽  
Vol 103 (20) ◽  
pp. 203501 ◽  
Author(s):  
Uio-Pu Chiou ◽  
Jia-Min Shieh ◽  
Chih-Chao Yang ◽  
Wen-Hsien Huang ◽  
Yo-Tsung Kao ◽  
...  

2018 ◽  
Vol 39 (2) ◽  
pp. 196-199 ◽  
Author(s):  
Lei Lu ◽  
Zhihe Xia ◽  
Jiapeng Li ◽  
Zhuoqun Feng ◽  
Sisi Wang ◽  
...  

2006 ◽  
Vol 910 ◽  
Author(s):  
Andew Flewitt ◽  
Shufan Lin ◽  
William I Milne ◽  
Ralf B Wehrspohn ◽  
Martin J Powell

AbstractIt has been widely observed that thin film transistors (TFTs) incorporating an hydrogenated amorphous silicon (a-Si:H) channel exhibit a progressive shift in their threshold voltage with time upon application of a gate bias. This is attributed to the creation of metastable defects in the a-Si:H which can be removed by annealing the device at elevated temperatures with no bias applied to the gate, causing the threshold voltage to return to its original value. In this work, the defect creation and removal process has been investigated using both fully hydrogenated and fully deuterated amorphous silicon (a-Si:D) TFTs. In both cases, material was deposited by rf plasma enhanced chemical vapour deposition over a range of gas pressures to cover the a-g transition. The variation in threshold voltage as a function of gate bias stressing time, and annealing time with no gate bias, was measured. Using the thermalisation energy concept, it has been possible to quantitatively determine the distribution of energies required for defect creation and removal as well as the associated attempt-to-escape frequencies. The defect creation and removal process in a-Si:H is then discussed in the light of these results.


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