scholarly journals A 2.4 GHz 2.9 mW Zigbee RF Receiver with Current-Reusing and Function-Reused Mixing Techniques

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 697
Author(s):  
Zhikuang Cai ◽  
Mingmin Shi ◽  
Shanwen Hu ◽  
Zixuan Wang
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Signal Strength ◽  
Low Noise ◽  
Cmos Process ◽  
Peak Detector ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Mixing Techniques ◽  
And Function

This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

CMOS Amplifier for Neural Signal Recording Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1279-1284
Author(s):  
Zhang Zhang ◽  
Zheng Xi Cheng ◽  
Yi Wei Zhuang
Keyword(s):  
Low Noise ◽  
Cmos Process ◽  
Differential Mode ◽  
Neural Signal ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Voltage Range ◽  
Cmos Amplifier ◽  
Signal Recording ◽  
Neural Signal Recording

A low power low noise CMOS amplifier with integrated filter for neural signal recording is designed and fabricated with CSMC 0.5 μm CMOS process. DC offsets introduced by electrode-tissue interface are rejected through a feedback low-pass filter. The bandwidth of the amplifier is in 3.5Hz-5.5KHz range, and the gain is about 48dB in the midband. AC input differential mode voltage range is 10mV, and DC input differential mode voltage range is 180mV. The amplifier can accommodate 180mV DC offsets drift and 10mV neural spikes. The neural probe array is integrated directly on the surface of the amplifier array chip, and is tested in saline solution, and also is implanted in rats in vivo , the results of the experiments show that the amplifier is suitable for neural signal recording. The power dissipation is about 14μW while consuming 0.16 mm2 of chip area, which satisfies implantable devices requirements.

scholarly journals Design consideration in low dropout voltage regulator for batteryless power management unit

2019 ◽  
Vol 8 (4) ◽  
Author(s):  
Mohamad Khairul bin Mohd Kamel ◽  
Yan Chiew Wong
Keyword(s):  
System Development ◽  
Maximum Load ◽  
Open Loop ◽  
Low Noise ◽  
Green Technology ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Process Technology ◽  
Pass Filter ◽  
Low Pass Filter

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

scholarly journals 0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7343
Author(s):  
Montree Kumngern ◽  
Nattharinee Aupithak ◽  
Fabian Khateb ◽  
Tomasz Kulej
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Subthreshold Region ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Multiple Input ◽  
Low Pass ◽  
Fifth Order

This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

scholarly journals A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 831 ◽  
Author(s):  
Jingyu Han ◽  
Yu Jiang ◽  
Guiliang Guo ◽  
Xu Cheng
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Open Loop ◽  
Low Noise ◽  
Pass Filter ◽  
Filter Order ◽  
High Linearity ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Analog Baseband

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

scholarly journals A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier

2021 ◽  
Vol 11 (17) ◽  
pp. 7982
Author(s):  
Gyuri Choi ◽  
Hyunwoo Heo ◽  
Donggeun You ◽  
Hyungseup Kim ◽  
Kyeongsik Nam ◽  
...  
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Readout Circuit ◽  
Output Stage ◽  
Current Feedback ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Folded Cascode

In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

scholarly journals A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1143
Author(s):  
Quanzhen Duan ◽  
Weidong Li ◽  
Shengming Huang ◽  
Yuemin Ding ◽  
Zhen Meng ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Input Voltage ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Chip Area ◽  
Linear Regulator

A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

Design of an Active-Gm-RC Reconfigurable Filter for the Multi-Mode Receiver

2013 ◽  
Vol 364 ◽  
pp. 458-462
Author(s):  
Lei Qian ◽  
Xiang Ning Fan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Frequency Offset ◽  
Cmos Process ◽  
Rf Cmos ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Rc Structure ◽  
Low Pass ◽  
Multi Mode

Based on TSMC 0.18m RF CMOS process a reconfigurable low-pass filter (LPF) is presented in this paper. The LPF adopts active-Gm-RC structure. By manually adjusting the capacitor arrays, the LPF can switch working mode and correct frequency offset caused by process deviation. The pre-layout simulation shows that with 1.8V power supply, the bandwidth ranges from 1.4MHz to 9.8MHz with a step of 1.4MHz. The out of band attenuation is about-80dB/10 octave and the power consumption is 0.43mW .

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

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