scholarly journals A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier

2021 ◽  
Vol 11 (17) ◽  
pp. 7982
Author(s):  
Gyuri Choi ◽  
Hyunwoo Heo ◽  
Donggeun You ◽  
Hyungseup Kim ◽  
Kyeongsik Nam ◽  
...  
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Readout Circuit ◽  
Output Stage ◽  
Current Feedback ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Folded Cascode

In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

A 3.6 μW 60 nV/sqrtHz Capacitively-Coupled Instrumentation Amplifier for Biopotential Signal Recordings

2015 ◽  
Vol 24 (06) ◽  
pp. 1550089 ◽  
Author(s):  
Yin Zhou ◽  
Xiaobo Wu ◽  
Peng Sun ◽  
Menglian Zhao
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Frequency Noise ◽  
Noise Power ◽  
Current Feedback ◽  
Common Mode ◽  
Capacitively Coupled ◽  
Offset Voltage

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply.

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

HIGH INDUCTANCE COIL EMBEDDED ON MAGNETIC SENSOR CHIP FOR BIOMAGNETIC SIGNAL MEASUREMENTS

2013 ◽  
Vol 27 (26) ◽  
pp. 1350159
Author(s):  
HYUNJUNE LYU ◽  
JUN RIM CHOI
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Magnetic Sensor ◽  
Oxide Semiconductor ◽  
Sensor Chip ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Current Feedback ◽  
Pass Filter ◽  
Inductance Coil

For the purpose of biomagnetic measurements, a magnetic sensor chip is manufactured using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process. A high-inductance coil and an instrumentation amplifier (IA) are embedded on this chip. The embedded high-inductance coil sensor contains suitable sensitivity and bandwidth for biomagnetic measurements, and is designed via electromagnetic field simulation. A low-gm operational transconductance amplifier (OTA) is also implemented on the chip to reduce the transconductance value. The output signal sensitivity of the magnetic sensor chip is 3.25 fT/μV, and the output reference noise is [Formula: see text]. The instrumentation amplifier is designed to minimize the magnetic signal noise using current feedback and a band-pass filter (BPF) with a bandwidth between 0.5 kHz and 5 kHz. The common-mode rejection ratio (CMRR) is measured at 117.5 dB by the Multi-Project Chip test. The proposed magnetic sensor chip is designed such that the input reference noise is maintained below 0.87 μV.

CMOS Amplifier for Neural Signal Recording Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1279-1284
Author(s):  
Zhang Zhang ◽  
Zheng Xi Cheng ◽  
Yi Wei Zhuang
Keyword(s):  
Low Noise ◽  
Cmos Process ◽  
Differential Mode ◽  
Neural Signal ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Voltage Range ◽  
Cmos Amplifier ◽  
Signal Recording ◽  
Neural Signal Recording

A low power low noise CMOS amplifier with integrated filter for neural signal recording is designed and fabricated with CSMC 0.5 μm CMOS process. DC offsets introduced by electrode-tissue interface are rejected through a feedback low-pass filter. The bandwidth of the amplifier is in 3.5Hz-5.5KHz range, and the gain is about 48dB in the midband. AC input differential mode voltage range is 10mV, and DC input differential mode voltage range is 180mV. The amplifier can accommodate 180mV DC offsets drift and 10mV neural spikes. The neural probe array is integrated directly on the surface of the amplifier array chip, and is tested in saline solution, and also is implanted in rats in vivo , the results of the experiments show that the amplifier is suitable for neural signal recording. The power dissipation is about 14μW while consuming 0.16 mm2 of chip area, which satisfies implantable devices requirements.

scholarly journals A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

2018 ◽  
Vol 2018 ◽  
pp. 1-10
Author(s):  
Guo-Ming Sung ◽  
Hsin-Kwang Wang ◽  
Leenendra Chowdary Gunnam
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Maximum Output ◽  
Hall Voltage ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
One Dimensional ◽  
Macro Model

This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs) to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

scholarly journals Design consideration in low dropout voltage regulator for batteryless power management unit

2019 ◽  
Vol 8 (4) ◽  
Author(s):  
Mohamad Khairul bin Mohd Kamel ◽  
Yan Chiew Wong
Keyword(s):  
System Development ◽  
Maximum Load ◽  
Open Loop ◽  
Low Noise ◽  
Green Technology ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Process Technology ◽  
Pass Filter ◽  
Low Pass Filter

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

scholarly journals A 2.4 GHz 2.9 mW Zigbee RF Receiver with Current-Reusing and Function-Reused Mixing Techniques

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 697
Author(s):  
Zhikuang Cai ◽  
Mingmin Shi ◽  
Shanwen Hu ◽  
Zixuan Wang
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Signal Strength ◽  
Low Noise ◽  
Cmos Process ◽  
Peak Detector ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Mixing Techniques ◽  
And Function

This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW.

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