scholarly journals A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 831 ◽  
Author(s):  
Jingyu Han ◽  
Yu Jiang ◽  
Guiliang Guo ◽  
Xu Cheng
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Open Loop ◽  
Low Noise ◽  
Pass Filter ◽  
Filter Order ◽  
High Linearity ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Analog Baseband

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

scholarly journals A 2.4 GHz 2.9 mW Zigbee RF Receiver with Current-Reusing and Function-Reused Mixing Techniques

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 697
Author(s):  
Zhikuang Cai ◽  
Mingmin Shi ◽  
Shanwen Hu ◽  
Zixuan Wang
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Signal Strength ◽  
Low Noise ◽  
Cmos Process ◽  
Peak Detector ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Mixing Techniques ◽  
And Function

This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW.

Neural mechanisms of adaptive gain control in a joint control loop: muscle force and motoneuronal activity

1997 ◽  
Vol 200 (9) ◽  
pp. 1383-1402 ◽  
Author(s):  
R Kittmann
Keyword(s):  
Muscle Force ◽  
Gain Control ◽  
Open Loop ◽  
Chordotonal Organ ◽  
Joint Control ◽  
Modulation Amplitude ◽  
Control Loop ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Change In Mean

An adaptive gain control system of a proprioceptive feedback system, the femur­tibia control loop, is investigated. It enables the joint control loop to work with a high gain but it prevents instability oscillations. In the inactive stick insect, the realisation of specific changes in gain is described for tibial torque, for extensor tibiae muscle force and for motoneuronal activity. In open-loop experiments, sinusoidal stimuli are applied to the femoral chordotonal organ (fCO). Changes in gain that depend on fCO stimulus parameters (such as amplitude, frequency and repetition rate), are investigated. Furthermore, spontaneous and touch-induced changes in gain that resemble the behavioural state of the animal are described. Changes in gain in motoneurones are always realised as changes in the amplitude of modulation of their discharge frequency. Nevertheless, depending on the stimulus situation, two different mechanisms underlie gain changes in motoneurones. (i) Changes in gain can be based on changes in the strength of the sensorimotor pathways that transmit stimulus-modulated information from the fCO to the motoneurones. (ii) Changes in gain can be based on changes in the mean activity of a motoneurone by means of its spike threshold: when, during the modulation, the discharge of a motoneurone is inhibited for part of the stimulus cycle, then a change in mean activity subsequently causes a change in modulation amplitude and gain. A new neuronal mechanism is described that helps to compensate the low-pass filter characteristics of the muscles by an increased activation, especially by a sharper distribution of spikes in the stimulus cycle at high fCO stimulus frequencies.

scholarly journals W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

2019 ◽  
Vol 30 ◽  
pp. 01006
Author(s):  
Alexander Kozhemyakin ◽  
Ivan Kravchenko
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Design Flow ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Fundamental Oscillation ◽  
Simulation Results

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

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