Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 813 ◽  
Author(s):  
Leonid Kladovščikov ◽  
Marijan Jurgo ◽  
Romualdas Navickas
Keyword(s):  
Cmos Technology ◽  
Test System ◽  
Oxide Semiconductor ◽  
Analog Filters ◽  
Detection Range ◽  
Active Analog ◽  
Parametric Faults ◽  
Self Test ◽  
Built In Self Test ◽  
Catastrophic Faults

In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

2013 ◽  
Vol 61 (8) ◽  
pp. 3083-3098 ◽  
Author(s):  
Sang Young Kim ◽  
Ozgur Inac ◽  
Choul-Young Kim ◽  
Donghyup Shin ◽  
Gabriel M. Rebeiz
Keyword(s):  
Phased Array ◽  
Test System ◽  
Self Test ◽  
Built In Self Test ◽  
Array Receiver

scholarly journals BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

2018 ◽  
Vol 1 (4) ◽  
Author(s):  
Hadi Jahanirad ◽  
Hanieh Karam
Keyword(s):  
Cmos Technology ◽  
Test Methods ◽  
Leakage Power ◽  
Digital Systems ◽  
Area Overhead ◽  
Logic Block ◽  
Fpga Chip ◽  
Simulation Results ◽  
Self Test ◽  
Built In Self Test

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

scholarly journals Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

2022 ◽  
Author(s):  
Benjamin Kommey ◽  
Ernest Addo ◽  
Jepthah Yankey ◽  
Andrew Agbemenu ◽  
Eric Tchao ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Synthesizer ◽  
Complementary Metal Oxide Semiconductor ◽  
External Input ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
Very High Frequency ◽  
Low Area ◽  
Self Test ◽  
Built In Self Test

Abstract This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

scholarly journals A Built-in Self-Test System for External DRAM

2020 ◽  
pp. 80-87
Author(s):  
Gor Abgaryan
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Efficiency ◽  
Random Access ◽  
Test System ◽  
Mass Storage ◽  
Access Memory ◽  
Yield And Quality ◽  
Self Test ◽  
Built In Self Test

In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.

scholarly journals CMOS Analog Filter Design for Very High Frequency Applications

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 362 ◽  
Author(s):  
Luis Abraham Sánchez-Gaspariano ◽  
Carlos Muñiz-Montero ◽  
Jesús Manuel Muñoz-Pacheco ◽  
Carlos Sánchez-López ◽  
Luz del Carmen Gómez-Pavón ◽  
...  
Keyword(s):  
High Frequency ◽  
Filter Design ◽  
Notch Filter ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Reduced Form ◽  
Analog Filters ◽  
Analog Filter ◽  
Very High Frequency ◽  
Very High

A design strategy for the synthesis of high-selectivity/low-order analog filters in Complementary Metal-Oxide-Semiconductor (CMOS) technology for very high frequency (VHF) applications is presented. The methodology for the reconstitution of a given transfer function by means of Signal Flow Graphs (SFG) manipulation in canonical form is proposed leading to a fully differential g m -C biquad filter. As a practical example, the design of a notch filter intended to suppress interferers in the lower sideband (400 MHz) of the Medical Implant Communication Service (MICS), in single-poly, 6-metal layers; Mixed-Signal/RF 0.18 µm CMOS technology is realized. To compare the performance of the proposal with some other solution, the design of a 7th order elliptic notch filter based on Frequency Dependent Negative Resistors (FDNRs) was also accomplished. The attained simulation results prove that the proposal is competitive compared to the FDNR solution and some other state-of-the-art filters reported in the literature. The most salient features of the proposed notch biquad include: the selectivity, whose value is comparable to that of a 7th order elliptic approach and some other 3rd order filters; a high-frequency operation without resonators; linearity, with a +15 dBm I I P 3 ; a reduced form factor with a total occupied area of 0.004282 mm2 and mostly a low design complexity.

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