FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA

With the emerging cloud-computing development, FPGAs are being integrated with cloud servers for higher performance. Recently, it has been explored to enable multiple users to share the hardware resources of a remote FPGA, i.e., to execute their own applications simultaneously. Although being a promising technique, multi-tenant FPGA unfortunately brings its unique security concerns. It has been demonstrated that the capacitive crosstalk between FPGA long-wires can be a side-channel to extract secret information, giving adversaries the opportunity to implement crosstalk-based side-channel attacks. Moreover, recent work reveals that medium-wires and multiplexers in configurable logic block (CLB) are also vulnerable to crosstalk-based information leakage. In this work, we propose FPGAPRO: a defense framework leveraging P lacement, R outing, and O bfuscation to mitigate the secret leakage on FPGA components, including long-wires, medium-wires, and logic elements in CLB. As a user-friendly defense strategy, FPGAPRO focuses on protecting the security-sensitive instances meanwhile considering critical path delay for performance maintenance. As the proof-of-concept, the experimental result demonstrates that FPGAPRO can effectively reduce the crosstalk-caused side-channel leakage by 138 times. Besides, the performance analysis shows that this strategy prevents the maximum frequency from timing violation.

Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.

Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.

Objectification of the evaluation of a pharmacological test with alpha-adrenergic blocking agents during uroflowmetry

The tactics of treating dysuric disorders are largely determined by the pathophysiological and morpho-clinical basis: infravesical obstruction, impaired bladder contractility, complex neurogenic urination disorders, etc. Among the diseases that most often cause infravesical obstruction in men, the most common pathologies are benign prostatic hyperplasia, prostate cancer, prostate sclerosis, obstructive processes of the bladder neck (contractures, fibrosis), urethral strictures of various etiologies. The use of a comprehensive urodynamic study makes it possible to differentiate the causes of urinary disorders. One of the most common and non-invasive methods used in the urologist’s clinical practice is uroflowmetry. The use of the fuzzy logic algorithm described in the article for making a decision on the presence of obstructive urination allows one to assess the urodynamic situation using the home uroflow monitoring technique. Analytical urodynamics in conjunction with the fuzzy logic block increases the accuracy of describing the examination results, and the introduction of the proposed model into the software simplifies the work with diagnostic urological equipment and increases the efficiency of the examination.

Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization

An Efficient tunable subthreshold logic circuit planned by utilizing adaptive feedback equalization circuit. This circuit utilized in the Ladner Fischer adder. This circuit utilized in a successive advanced logic circuit to moderate the cycle variety impacts and lessen the prevailing spillage energy part in the subthreshold area. Feedback equalizer circuit changes the switching edge of its inverter. It depends on the output of the flip-flop in the past cycle to lessen the charging and releasing season of the flip-flop's information capacitance. Besides, the more modest info capacitance of the feedback equalizer lessens the switching season of the last door in the combinational logic block. Likewise present point by point energy-performance models of the adaptive feedback equalizer circuit.

Merging and Prioritizing Optimization in Block I/O Scheduling of Disk Storage

I/O merging optimization at the block I/O layer of disk storage is widely adopted to reduce I/O response time. But it may result in certain overhead of merging judgment in the case of a large number of concurrent I/O requests accessing disk storage, and place negative effects on the response of small requests. This paper proposes a divide and conquer scheduling scheme at the block layer of I/O stack, to satisfy a large number of concurrent I/O requests with less I/O response time and ensure the fairness of each request response by decreasing the average I/O latency. First, we propose a horizontal visibility graph-based approach to cluster relevant block requests, according to their offsets (i.e., logic block numbers). Next, it carries out the optimization operation of merging consecutive block I/O requests within each cluster, as only these requests in the same cluster are most likely to be issued by a specific application. Then, we have introduced the functionality of merging judgment when performing merging optimization to effectively guarantee the average I/O response time. After that, the merged requests in the queue will be reordered on the basis of their priorities, to purposely cut down the average I/O response time. Finally, the prioritized requests are supposed to be delivered to the disk storage, for being serviced. Through a series of experiments, we show that compared to the benchmark, the newly proposed scheme can not only cut down the I/O response time by more than 18.2%, but also decrease the average I/O response time up to 71.7%.

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

APLIKASI STOCK OPNAME PRODUK KECANTIKAN KOSÉ BERBASIS ANDROID

Stock opname is an effort to control the turnover of a product so as not to deviate. The implementation of stock opname is inseparable from the support of the information system, therefore the aim of this study is to analyze the stock opname process of KOSÉ beauty product and to create a suitable application to facilitate the process. Analysis performed using the System Development Life Cycle. Data collection was obtained through interviews, observations, sampling and literature. The application design uses the Object Oriented Programming method. Testing application uses the blackbox method. The results of this study are an android application is made through Kodular and connected to the realtime database of Firebase, but the implementation of the application still has flaws in logic block-coding.