scholarly journals A Built-in Self-Test System for External DRAM

2020 ◽  
pp. 80-87
Author(s):  
Gor Abgaryan
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Efficiency ◽  
Random Access ◽  
Test System ◽  
Mass Storage ◽  
Access Memory ◽  
Yield And Quality ◽  
Self Test ◽  
Built In Self Test

In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.

Design and Implementation of FSM Based MBIST using March Algorithm

2020 ◽  
pp. 18-21
Author(s):  
P Aishwarya , Dr. K Deepti
Keyword(s):  
Integrated Circuits ◽  
Finite State Machine ◽  
Random Access ◽  
Automatic Test Equipment ◽  
Access Memory ◽  
Machine Model ◽  
Research Article ◽  
Finite State ◽  
Self Test ◽  
Built In Self Test

The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.

scholarly journals BIST Architecture for Magnetic Memories

2020 ◽  
pp. 88-95
Author(s):  
Armen Babayan
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Test Solution ◽  
Access Memory ◽  
Magnetic Random Access Memory ◽  
Emerging Memory ◽  
Self Test ◽  
Built In Self Test

Magnetic random-access memory (MRAM) is one of the emerging memory technologies, which can be considered as the next universal memory because of its good parameters. Nevertheless, this type of memory is not guaranteed from defects and it is very important to understand the fault typology and develop a test solution that addresses these faults. In this paper a Built-in Self-Test (BIST) solution is presented, which is specifically tailored for MRAMs and efficiently deals with MRAM specific faults.

scholarly journals BIST Architecture for Magnetic Memories

2020 ◽  
pp. 88-95
Author(s):  
Armen Babayan
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Test Solution ◽  
Access Memory ◽  
Magnetic Random Access Memory ◽  
Emerging Memory ◽  
Self Test ◽  
Built In Self Test

Magnetic random-access memory (MRAM) is one of the emerging memory technologies, which can be considered as the next universal memory because of its good parameters. Nevertheless, this type of memory is not guaranteed from defects and it is very important to understand the fault typology and develop a test solution that addresses these faults. In this paper a Built-in Self-Test (BIST) solution is presented,which is specifically tailored for MRAMs and efficiently deals with MRAM specific faults.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

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